Chinese Science Bulletin

, Volume 55, Issue 35, pp 4089–4093 | Cite as

An AP SoC for a unified architecture

  • XuBang ShenEmail author
  • CuiHua Zhao
Article Computer Science & Technology


An instruction level parallel computing paradigm and a unified architecture for an array processor (AP) on a chip (SoC) are presented in this paper. Here “APU SoC” is short for “an AP SoC for the unified architecture”. The MISD/MIMD architecture for instruction level parallel computing is unified with the SIMD architecture for data level parallel computing. As a result, all the computing can be implemented on an APU SoC. The APU SoC offers the rationale of an array structure for development in current technology, yet simplicity for the hardware (chip) and software (program) parallel designs. Just as a single processor chip can replace many function module chips, the APU SoC can replace the single-core/multi-core/many-core CPU chip for TLP computing and the ASIC/ASSP/FPGA/RC device array chip for Operation Level Parallel computing.




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Copyright information

© Science China Press and Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  1. 1.Xi’an Microelectronics Research InstituteXi’anChina

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