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Architecture-circuit-technology co-optimization for resistive random access memory-based computation-in-memory chips

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Abstract

Computation-in-memory (CIM) chips offer an energy-efficient approach to artificial intelligence computing workloads. Resistive random-access memory (RRAM)-based CIM chips have proven to be a promising solution for overcoming the von Neumann bottleneck. In this paper, we review our recent studies on the architecture-circuit-technology co-optimization of scalable CIM chips and related hardware demonstrations. To further minimize data movements between memory and computing units, architecture optimization methods have been introduced. Then, we propose a device-architecture-algorithm co-design simulator to provide guidelines for designing CIM systems. A physics-based compact RRAM model and an array-level analog computing model were embedded in the simulator. In addition, a CIM compiler was proposed to optimize the on-chip dataflow. Finally, research perspectives are proposed for future development.

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Acknowledgements

This work was supported by National Natural Science Foundation of China (Grant Nos. 92064001, 62025111, 92264201) and Beijing Advanced Innovation Center for Integrated Circuits.

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Authors and Affiliations

  1. School of Integrated Circuits, Beijing National Research Center for Information Science and Technology (BNRist), Tsinghua University, Beijing, 100084, China

    Yuyi Liu, Bin Gao, Jianshi Tang, Huaqiang Wu & He Qian

Authors
  1. Yuyi Liu
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  2. Bin Gao
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  3. Jianshi Tang
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  4. Huaqiang Wu
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  5. He Qian
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Corresponding author

Correspondence to Bin Gao.

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Liu, Y., Gao, B., Tang, J. et al. Architecture-circuit-technology co-optimization for resistive random access memory-based computation-in-memory chips. Sci. China Inf. Sci. 66, 200408 (2023). https://doi.org/10.1007/s11432-023-3785-8

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  • DOI: https://doi.org/10.1007/s11432-023-3785-8

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