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From lab to fab: path forward for 2D material electronics

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Abstract

The increasing demand for computation requires the development of energy-efficient logic devices with reduced dimensions. Owing to their atomic thickness, 2D semiconductors are expected to provide possible solutions at the sub-1 nm technology node. Furthermore, taking advantage of the van der Waals nature, the low-temperature back-end of line integration with silicon may occur in the near future. In this perspective, vital progress in material synthesis, device engineering, and integration technologies toward integrated circuits based on 2D materials is reviewed. The challenges and important milestones on the roadmap for the next decade toward the fab adoption of 2D materials are outlined. Particularly, performance, power, area, cost, and equipment for further technology development in this area are proposed as key metrics and enablers.

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References

  1. IEEE. International Roadmap for Devices and Systems (IRDS) 2021 Edition. 2021. https://irds.ieee.org/editions/2021

  2. Radisavljevic B, Radenovic A, Brivio J, et al. Single-layer MoS2 transistors. Nat Nanotech, 2011, 6: 147–150

    Article  Google Scholar 

  3. Yu Z, Pan Y, Shen Y, et al. Towards intrinsic charge transport in monolayer molybdenum disulfide by defect and interface engineering. Nat Commun, 2014, 5: 5290

    Article  Google Scholar 

  4. Lee Y H, Zhang X Q, Zhang W, et al. Synthesis of large-area MoS2 atomic layers with chemical vapor deposition. Adv Mater, 2012, 24: 2320–2325

    Article  Google Scholar 

  5. Zhou J, Lin J, Huang X, et al. A library of atomically thin metal chalcogenides. Nature, 2018, 556: 355–359

    Article  Google Scholar 

  6. Liu L, Li T, Ma L, et al. Uniform nucleation and epitaxy of bilayer molybdenum disulfide on sapphire. Nature, 2022, 605: 69–75

    Article  Google Scholar 

  7. Li W, Zhou J, Cai S, et al. Uniform and ultrathin high-κ gate dielectrics for two-dimensional electronic devices. Nat Electron, 2019, 2: 563–571

    Article  Google Scholar 

  8. Lee T-E, Su Y-C, Lin B-J, et al. Nearly ideal subthreshold swing in monolayer MoS2 top-gate nFETs with scaled EOT of 1 nm. In: Proceedings of 2022 International Electron Devices Meeting (IEDM), San Francisco, 2022

  9. Liu K, Jin B, Han W, et al. A wafer-scale van der Waals dielectric made from an inorganic molecular crystal film. Nat Electron, 2021, 4: 906–913

    Article  Google Scholar 

  10. Huang J K, Wan Y, Shi J, et al. High-κ perovskite membranes as insulators for two-dimensional transistors. Nature, 2022, 605: 262–267

    Article  Google Scholar 

  11. Lee G H, Cui X, Kim Y D, et al. Highly stable, dual-gated MoS2 transistors encapsulated by hexagonal boron nitride with gate-controllable contact, resistance, and threshold voltage. ACS Nano, 2015, 9: 7019–7026

    Article  Google Scholar 

  12. Li T, Tu T, Sun Y, et al. A native oxide high-κ gate dielectric for two-dimensional electronics. Nat Electron, 2020, 3: 473–478

    Article  Google Scholar 

  13. Wang Y, Kim J C, Li Y, et al. P-type electrical contacts for 2D transition-metal dichalcogenides. Nature, 2022, 610: 61–66

    Article  Google Scholar 

  14. Li W, Gong X, Yu Z, et al. Approaching the quantum limit in two-dimensional semiconductor contacts. Nature, 2023, 613: 274–279

    Article  Google Scholar 

  15. Sebastian A, Pendurthi R, Choudhury T H, et al. Benchmarking monolayer MoS2 and WS2 field-effect transistors. Nat Commun, 2021, 12: 693

    Article  Google Scholar 

  16. Desai S B, Madhvapathy S R, Sachid A B, et al. MoS2 transistors with 1-nanometer gate lengths. Science, 2016, 354: 99–102

    Article  Google Scholar 

  17. Tong L, Wan J, Xiao K, et al. Heterogeneous complementary field-effect transistors based on silicon and molybdenum disulfide. Nat Electron, 2023, 6: 37–44

    Google Scholar 

  18. Wachter S, Polyushkin D K, Bethge O, et al. A microprocessor based on a two-dimensional semiconductor. Nat Commun, 2017, 8: 14948

    Article  Google Scholar 

  19. Polyushkin D K, Wachter S, Mennel L, et al. Analogue two-dimensional semiconductor electronics. Nat Electron, 2020, 3: 486–491

    Article  Google Scholar 

  20. Marega G M, Zhao Y, Avsar A, et al. Logic-in-memory based on an atomically thin semiconductor. Nature, 2020, 587: 72–77

    Article  Google Scholar 

  21. Mennel L, Symonowicz J, Wachter S, et al. Ultrafast machine vision with 2D material neural network image sensors. Nature, 2020, 579: 62–66

    Article  Google Scholar 

  22. Meng W, Xu F, Yu Z, et al. Three-dimensional monolithic micro-LED display driven by atomically thin transistor matrix. Nat Nanotechnol, 2021, 16: 1231–1236

    Article  Google Scholar 

  23. Yu Z, Ning H, Cheng C-C, et al. Reliability of ultrathin high-κ dielectrics on chemical-vapor deposited 2D semiconductors. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2020

  24. Ning H K, Yu Z H, Zhang Q T, et al. An in-memory computing architecture based on a duplex two-dimensional material structure for in situ machine learning. Nat Nanotechnol, 2023. doi: https://doi.org/10.1038/s41565-023-01343-0

  25. Kim K S, Lee D, Chang C S, et al. Non-epitaxial single-crystal 2D material growth by geometric confinement. Nature, 2023, 614: 88–94

    Article  Google Scholar 

  26. Wan Y, Li E, Yu Z, et al. Low-defect-density WS2 by hydroxide vapor phase deposition. Nat Commun, 2022, 13: 4149

    Article  Google Scholar 

  27. Li T, Guo W, Ma L, et al. Epitaxial growth of wafer-scale molybdenum disulfide semiconductor single crystals on sapphire. Nat Nanotechnol, 2021, 16: 1201–1207

    Article  Google Scholar 

  28. Wang J, Xu X, Cheng T, et al. Dual-coupling-guided epitaxial growth of wafer-scale single-crystal WS2 monolayer on vicinal a-plane sapphire. Nat Nanotechnol, 2022, 17: 33–38

    Article  Google Scholar 

  29. Kappera R, Voiry D, Yalcin S E, et al. Phase-engineered low-resistance contacts for ultrathin MoS2 transistors. Nat Mater, 2014, 13: 1128–1134

    Article  Google Scholar 

  30. Wang Q, Tang J, Li X, et al. Layer-by-layer epitaxy of multi-layer MoS2 wafers. Natl Sci Rev, 2022, 9: nwac077

    Article  Google Scholar 

  31. Qiu H, Xu T, Wang Z, et al. Hopping transport through defect-induced localized states in molybdenum disulphide. Nat Commun, 2013, 4: 2642

    Article  Google Scholar 

  32. Zhang Z, Chen P, Duan X, et al. Robust epitaxial growth of two-dimensional heterostructures, multiheterostructures, and superlattices. Science, 2017, 357: 788–792

    Article  Google Scholar 

  33. Sahoo P K, Memaran S, Xin Y, et al. One-pot growth of two-dimensional lateral heterostructures via sequential edge-epitaxy. Nature, 2018, 553: 63–67

    Article  Google Scholar 

  34. Liu Y, Weiss N O, Duan X, et al. Van der Waals heterostructures and devices. Nat Rev Mater, 2016, 1: 16042

    Article  Google Scholar 

  35. Li J, Yang X, Liu Y, et al. General synthesis of two-dimensional van der Waals heterostructure arrays. Nature, 2020, 579: 368–374

    Article  Google Scholar 

  36. Kelleher A B. Celebrating 75 years of the transistor A look at the evolution of Moore’s Law innovation. In: Proceedings of 2022 International Electron Devices Meeting (IEDM), San Francisco, 2022

  37. Dorow C J, Penumatcha A, Kitamura A, et al. Gate length scaling beyond Si: mono-layer 2D channel FETs robust to short channel effects. In: Proceedings of 2022 International Electron Devices Meeting (IEDM), San Francisco, 2022

  38. Pal A, Mishra V, Weber J, et al. Characterization and closed-form modeling of edge/top/hybrid metal-2D semiconductor contacts. In: Proceedings of 2022 International Electron Devices Meeting (IEDM), San Francisco, 2022

  39. O’Brien K P, Dorow C J, Penumatcha A, et al. Advancing 2D monolayer CMOS through contact, channel and interface engineering. In: Proceedings of 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2021

  40. Yang N, Lin Y C, Chuu C-P, et al. Computational screening and multiscale simulation of barrier-free contacts for 2D semiconductor pFETs. In: Proceedings of 2022 International Electron Devices Meeting (IEDM), San Francisco, 2022

  41. Chung Y-Y, Chou B-J, Hsu C-F, et al. First demonstration of GAA monolayer-MoS2 nanosheet nFET with 410 µA µm ID 1V VD at 40 nm gate length. In: Proceedings of 2022 International Electron Devices Meeting (IEDM), San Francisco, 2022

  42. Chou A-S, Lin Y-T, Lin Y C, et al. High-performance monolayer WSe2 p/n FETs via antimony-platinum modulated contact technology towards 2D CMOS electronics. In: Proceedings of 2022 International Electron Devices Meeting (IEDM), San Francisco, 2022

  43. Hung T Y T, Li M-Z, Yun W S, et al. pMOSFET with CVD-grown 2D semiconductor channel enabled by ultra-thin and fab-compatible spacer doping. In: Proceedings of 2022 International Electron Devices Meeting (IEDM), San Francisco, 2022

  44. Lee T-E, Su Y-C, Lin B-J, et al. Nearly ideal subthreshold swing in monolayer MoS2 top-gate nFETs with scaled EOT of 1 nm. In: Proceedings of 2022 International Electron Devices Meeting (IEDM), San Francisco, 2022

  45. Smets Q, Groven B L D, Caymax M, et al. Ultra-scaled MOCVD MoS2 MOSFETs with 42 nm contact pitch and 250 µA/µm drain current. In: Proceedings of 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2019

  46. Wu X, Cott D, Lin Z, et al. Dual gate synthetic MoS2 MOSFETs with 4.56 µF/cm2 channel capacitance, 320 µS/µm Gm and 420 µA/µm Id at 1V Vd/100 nm Lg. In: Proceedings of 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2021

  47. Smets Q, Schram T, Verreck D, et al. Scaling of double-gated WS2 FETs to sub-5nm physical gate length fabricated in a 300 mm FAB. In: Proceedings of 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2021

  48. Shi Y, Groven B L D, Smets Q, et al. Superior electrostatic control in uniform monolayer MoS2 scaled transistors via in-situ surface smoothening. In: Proceedings of 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2021

  49. Illarionov Y Y, Banshchikov A G, Polyushkin D K, et al. Ultrathin calcium fluoride insulators for two-dimensional field-effect transistors. Nat Electron, 2019, 2: 230–235

    Article  Google Scholar 

  50. Liu Y, Guo J, Zhu E, et al. Approaching the Schottky-Mott limit in van der Waals metal-semiconductor junctions. Nature, 2018, 557: 696–700

    Article  Google Scholar 

  51. Wang Y, Kim J C, Wu R J, et al. Van der Waals contacts between three-dimensional metals and two-dimensional semiconductors. Nature, 2019, 568: 70–74

    Article  Google Scholar 

  52. Shen P C, Su C, Lin Y, et al. Ultralow contact resistance between semimetal and monolayer semiconductors. Nature, 2021, 593: 211–217

    Article  Google Scholar 

  53. Lanza M, Smets Q, Huyghebaert C, et al. Yield, variability, reliability, and stability of two-dimensional materials based solid-state electronic devices. Nat Commun, 2020, 11: 5689

    Article  Google Scholar 

  54. Smets Q, Verreck D, Shi Y, et al. Sources of variability in scaled MoS2 FETs. In: Proceedings of 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2020

  55. Wu F, Tian H, Shen Y, et al. Vertical MoS2 transistors with sub-1-nm gate lengths. Nature, 2022, 603: 259–264

    Article  Google Scholar 

  56. Huang X, Liu C, Tang Z, et al. High drive and low leakage current MBC FET with channel thickness 1.2 nm/0.6 nm. In: Proceedings of 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2020

  57. Xiong X, Tong A, Wang X, et al. Demonstration of vertically-stacked CVD MONOLAYER Channels: MoS2 nanosheets GAA-FET with Ion> 700 µA/µm and MoS2/WSe2 CFET. In: Proceedings of 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2021

  58. Xiong X, Liu S, Liu H, et al. Top-gate CVD WSe2 pFETs with record-high Id∼594 µA/µm, Gm∼244 µS/µm and WSe2/MoS2 CFET based half-adder circuit using monolithic 3D integration. In: Proceedings of 2022 International Electron Devices Meeting (IEDM), San Francisco, 2022

  59. Wang X, Chen X, Ma J, et al. Pass-transistor logic circuits based on wafer-scale 2D semiconductors. Adv Mater, 2022, 34: 2202472

    Article  Google Scholar 

  60. Liu L, Liu C, Jiang L, et al. Ultrafast non-volatile flash memory based on van der Waals heterostructures. Nat Nanotechnol, 2021, 16: 874–881

    Article  Google Scholar 

  61. Ma S, Wu T, Chen X, et al. An artificial neural network chip based on two-dimensional semiconductor. Sci Bull, 2022, 67: 270–277

    Article  Google Scholar 

  62. Schram T, Smets Q, Groven B, et al. WS2 transistors on 300 mm wafers with BEOL compatibility. In: Proceedings of the 47th European Solid-State Device Research Conference (ESSDERC), Leuven, 2017. 212–215

  63. Hwangbo S, Hu L, Hoang A T, et al. Wafer-scale monolithic integration of full-colour micro-LED display using MoS2 transistor. Nat Nanotechnol, 2022, 17: 500–506

    Article  Google Scholar 

  64. Zhao T, Guo J, Li T, et al. Substrate engineering for wafer-scale two-dimensional material growth: strategies, mechanisms, and perspectives. Chem Soc Rev, 2023, 52: 1650–1671

    Article  Google Scholar 

  65. Asselberghs I, Smets Q, Schram T, et al. Wafer-scale integration of double gated WS2-transistors in 300 mm Si CMOS fab. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2020

  66. Jiang J F, Xu L, Du L J, et al. Yttrium-induced phase-transition technology for forming perfect ohmic contact in two-dimensional MoS2 transistors. Research Square, 2023. doi: https://doi.org/10.21203/rs.3.rs-2508636/v1

  67. Schram T, Sutar S, Radu I, et al. Challenges of wafer-scale integration of 2D semiconductors for high-performance transistor circuits. Adv Mater, 2022, 34: 2109796

    Article  Google Scholar 

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Acknowledgements

This work was supported by National Key R&D Program of China (Grant Nos. 2022YFB4400100, 2020YFA0309600), National Natural Science Foundation of China (Grant Nos. T2221003, 61927808, 61734003, 61851401, 91964202, 62204124, 62204113, 12104330, 51861145202), Leading-Edge Technology Program of Jiangsu Natural Science Foundation (Grant No. BK20202005), Natural Science Foundation of Jiangsu Province (Grant No. BK20220773), Strategic Priority Research Program of the Chinese Academy of Sciences (Grant No. XDB30000000), Fundamental Research Funds for the Central Universities, China (Grant No. 2023300247), Key-Area Research and Development Program of Guangdong Province (Grant No. 2020B0101340001), Key Laboratory of Advanced Photonic and Electronic Materials, and Collaborative Innovation Center of Solid-State Lighting and Energy-Saving Electronics.

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Correspondence to Zhihao Yu or Xinran Wang.

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Ning, H., Yu, Z., Li, T. et al. From lab to fab: path forward for 2D material electronics. Sci. China Inf. Sci. 66, 160411 (2023). https://doi.org/10.1007/s11432-023-3752-3

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