Abstract
Post-layout simulation provides accurate guidance for analog circuit design, but post-layout performance is hard to be directly optimized at early design stages. Prior work on analog circuit sizing often utilizes pre-layout simulation results as the optimization objective. In this work, we propose a post-layout-simulation-driven (post-simulation-driven for short) analog circuit sizing framework that directly optimizes the post-layout simulation performance. The framework integrates automated layout generation into the optimization loop of transistor sizing and leverages a coupled Bayesian optimization algorithm to search for the best post-simulation performance. Experimental results demonstrate that our framework can achieve over 20% better post-layout performance in competitive time than manual design and the method that only considers pre-layout optimization.
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Acknowledgements
This work was supported in part by National Natural Science Foundation of China (Grant Nos. 62141404, 62034007) and 111 Project (Grant No. B18001). We would like to thank Kenuo XU for drawing Figure 1.
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Gao, X., Zhang, H., Ye, S. et al. Post-layout simulation driven analog circuit sizing. Sci. China Inf. Sci. 67, 142401 (2024). https://doi.org/10.1007/s11432-022-3878-5
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DOI: https://doi.org/10.1007/s11432-022-3878-5