Springer Nature is making SARS-CoV-2 and COVID-19 research free. View research | View latest news | Sign up for updates

Vertical SnS2/Si heterostructure for tunnel diodes

  • 75 Accesses

  • 1 Citations

Abstract

Tunneling FET (TFET) is considered as one of the most promising low-power electronic devices, however, suffers from the low drive current. Heterostructure TFET with low effective tunnel barrier height based on traditional 3D materials can obtain large tunnel current but deteriorated off-state current induced by the lattice mismatch. van der Waals heterostructure TFET based on 2D materials can obtain dangling-bond-free interface for suppressed off-state current but face the challenge of controllable and stable doping technology. As the critical building block of the TFET, tunnel diode based on the 2D/3D heterostructure is proposed in this study and experimentally demonstrated. Combination of the pristine interface of 2D materials and matured doping technology in the traditional 3D bulk materials, tunnel diodes based on the 2D/3D heterostructures are expected to realize low leakage current and high on current simultaneously, showing great potential in low-power electronics. The N+ SnS2/P+ Si heterostructure with effective tunnel barrier of 0.17 eV theoretically is considered for the first time and selected as the optimal material platform for tunnel diodes. The N+ SnS2/P+ Si tunnel diode demonstrated experimentally shows the high current density of 1 µA/µm2, which is the highest one among the reported tunnel diodes based on the 2D/group IV materials. The tunneling current is also confirmed by low-temperature measurements. This study shows the great potential of the 2D/3D heterostructure for low-power tunneling devices.

This is a preview of subscription content, log in to check access.

References

  1. 1

    Ionescu A M, Riel H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature, 2011, 479: 329–337

  2. 2

    Sarkar D, Xie X, Liu W, et al. A subthermionic tunnel field-effect transistor with an atomically thin channel. Nature, 2015, 526: 91–95

  3. 3

    Zhao Y, Wu C L, Huang Q Q, et al. A novel tunnel FET design through adaptive bandgap engineering with constant sub-threshold slope over 5 decades of current and high ION/IOFF ratio. IEEE Electron Device Lett, 2017, 38: 540–543

  4. 4

    Dey A W, Borg B M, Ganjipour B, et al. High-current GaSb/InAs(Sb) nanowire tunnel field-effect transistors. IEEE Electron Device Lett, 2013, 34: 211–213

  5. 5

    Liu Y, Weiss N O, Duan X D, et al. Van der Waals heterostructures and devices. Nat Rev Mater, 2016, 1: 16042

  6. 6

    Roy T, Tosun M, Cao X, et al. Dual-gated MoS2/WSe2 van der Waals tunnel diodes and transistors. ACS Nano, 2015, 9: 2071–2079

  7. 7

    Roy T, Tosun M, Hettick M, et al. 2D-2D tunneling field-effect transistors using WSe2/SnSe2 heterostructures. Appl Phys Lett, 2016, 108: 083111

  8. 8

    Xu J, Jia J Y, Lai S, et al. Tunneling field effect transistor integrated with black phosphorus-MoS2 junction and ion gel dielectric. Appl Phys Lett, 2017, 110: 033103

  9. 9

    Yan X, Liu C S, Li C, et al. Tunable SnSe2/WSe2 heterostructure tunneling field effect transistor. Small, 2017, 1701478

  10. 10

    Li X F, Gao T T, Wu Y Q. Development of two-dimensional materials for electronic applications. Sci China Inf Sci, 2016, 59: 061405

  11. 11

    Xie Q, Chen C, Liu M J, et al. Short-channel effects on the static noise margin of 6T SRAM composed of 2D semiconductor MOSFETs. Sci China Inf Sci, 2019, 62: 062404

  12. 12

    Krishnamoorthy S, Lee Ii E W, Lee C H, et al. High current density 2D/3D MoS2/GaN Esaki tunnel diodes. Appl Phys Lett, 2016, 109: 183505

  13. 13

    Zhang B X, An X, Liu P Q, et al. Improvement of thermal stability of nickel germanide using nitrogen plasma pretreatment for germanium-based technology. Sci China Inf Sci, 2018, 61: 109401

  14. 14

    Xu K, Cai Y H, Zhu W J. Esaki diodes based on 2-D/3-D heterojunctions. IEEE Trans Electron Devices, 2018, 65: 4155–4159

  15. 15

    McDonnell S, Addou R, Buie C, et al. Defect-dominated doping and contact resistance in MoS2. ACS Nano, 2014, 8: 2880–2888

  16. 16

    Schlaf R, Lang O, Pettenkofer C, et al. Band lineup of layered semiconductor heterointerfaces prepared by van der Waals epitaxy: charge transfer correction term for the electron affinity rule. J Appl Phys, 1999, 85: 2732–2753

  17. 17

    Fang N, Nagashio K. Accumulation-mode two-dimensional field-effect transistor: operation mechanism and thickness scaling rule. ACS Appl Mater Interfaces, 2018, 10: 32355–32364

  18. 18

    Jin Y, Keum D H, An S J, et al. A van der Waals homojunction: ideal p-n diode behavior in MoSe2. Adv Mater, 2015, 27: 5534–5540

  19. 19

    Doan M H, Jin Y, Adhikari S, et al. Charge transport in MoS2/WSe2 van der Waals heterostructure with tunable inversion layer. ACS Nano, 2017, 11: 3832–3840

  20. 20

    Bludau W, Onton A, Heinke W. Temperature dependence of the band gap of silicon. J Appl Phys, 1974, 45: 1846–1848

  21. 21

    Burton L A, Whittles T J, Hesp D, et al. Electronic and optical properties of single crystal SnS2: an earth-abundant disulfide photocatalyst. J Mater Chem A, 2016, 4: 1312–1318

  22. 22

    Huang Q Q, Huang R, Zhan Z, et al. A novel Si Tunnel FET with 36 mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2012. 187–190

Download references

Acknowledgements

This work was partly supported by National Natural Science Foundation of China (Grant Nos. 61421005, 61851401, 61822401, 61604006) and the 111 Project (Grant No. B18001).

Author information

Correspondence to Qianqian Huang or Ru Huang.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Jia, R., Huang, Q. & Huang, R. Vertical SnS2/Si heterostructure for tunnel diodes. Sci. China Inf. Sci. 63, 122401 (2020). https://doi.org/10.1007/s11432-019-9836-9

Download citation

Keywords

  • 2D/3D heterostructure
  • SnS2/Si
  • tunnel barrier
  • tunnel diode
  • energy-efficient