Transistor level SCA-resistant scheme based on fluctuating power logic

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References

  1. 1

    Saravanan P, Kalpana P. An energy efficient XOR gate implementation resistant to power analysis attacks. J Eng Sci Tech, 2015, 10: 1275–1292

    Google Scholar 

  2. 2

    Mangard S, Oswald E, Popp T. Power Analysis Attacks: Revealing the Secrets of Smart Cards. Berlin: Springer Science & Business Media,2008

    Google Scholar 

  3. 3

    Moradi A, Kirschbaum M, Eisenbarth T, et al. Masked dual-rail precharge logic encounters state-ofthe-art power analysis methods. IEEE Trans Very Large Scale Integr Syst, 2012, 20: 1578–1589

    Article  Google Scholar 

  4. 4

    Kawaguchi H, Sakurai T. A reduced clock-swing flipflop (RCSFF) for 63% power reduction. IEEE J Solid- State Circ, 1998, 33: 807–811

    Article  Google Scholar 

  5. 5

    Zhao P, Darwish T, Bayoumi M. High-performance and low power conditional discharge flip-flop. IEEE Trans Very Large Scale Integr Syst, 2004, 12: 477–484

    Article  Google Scholar 

Download references

Acknowledgements

This work was supported in part by National Natural Science Foundation of China (Grant Nos. 61173191, 61272491, 61309021, 61472357, 61571063), National Basic Research Program of China (973 Program) (Grant No. 2013CB338004), and Science and Technology on Communication Security Laboratory (Grant No. 9140C110602150C11053).

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Correspondence to Fan Zhang.

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The authors declare that they have no conflict of interest.

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Geng, L., Zhang, F., Shen, J. et al. Transistor level SCA-resistant scheme based on fluctuating power logic. Sci. China Inf. Sci. 60, 109401 (2017). https://doi.org/10.1007/s11432-016-9046-4

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