Design for manufacturability and reliability in extreme-scaling VLSI

Science China Information Sciences volume 59, Article number: 061406 (2016) Cite this article

Abstract

In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore’s law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.

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References

  1. 1

    Moore G E. Lithography and the future of Moore’s law. Proc SPIE, 1995, 2438: 2–17

    Article  Google Scholar 

  2. 2

    Pan D Z, Yu B, Gao J-R. Design for manufacturing with emerging nanolithography. IEEE Trans Comput Aided Des Integr Circ Syst, 2013, 32: 1453–1472

    Article  Google Scholar 

  3. 3

    Yu B, Pan D Z. Design for Manufacturability with Advanced Lithography. Springer, 2015

    Google Scholar 

  4. 4

    Reis R, Cao Y, Wirth G. Circuit Design for Reliability. Springer, 2014

    Google Scholar 

  5. 5

    Maricau E, Gielen G. Computer-aided analog circuit design for reliability in nanometer CMOS. IEEE J Emerg Sel Top Circ Syst, 2011, 1: 50–58

    Article  Google Scholar 

  6. 6

    Mallik A, Zuber P, Liu T T, et al. TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), Austin, 2013. 24: 1–24: 6

    Google Scholar 

  7. 7

    Liebmann L, Chu A, Gutwin P. The daunting complexity of scaling to 7nm without EUV: pushing DTCO to the extreme. Proc SPIE, 2015: 9427

    Google Scholar 

  8. 8

    Chava B, Rio D, Sherazi Y, et al. Standard cell design in N7: EUV vs. immersion. Proc SPIE, 2015: 9427

    Google Scholar 

  9. 9

    Taylor B, Pileggi L. Exact combinatorial optimization methods for physical design of regular logic bricks. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Diego, 2007. 344–349

    Google Scholar 

  10. 10

    Maly W, Lin Y W, Sadowska M M. OPC-free and minimally irregular IC design style. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Diego, 2007. 954–957

    Google Scholar 

  11. 11

    Zhang H B, Wong M D F, Chao K Y. On process-aware 1-D standard cell design. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Taipei, 2010. 838–842

    Google Scholar 

  12. 12

    Ryzhenko N, Burns S. Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Diego, 2011. 83–88

    Google Scholar 

  13. 13

    Wu P H, Lin M P, Chen T C, et al. 1-D cell generation with printability enhancement. IEEE Trans Comput Aided Des Integr Circ Syst, 2013, 32: 419–432

    Article  Google Scholar 

  14. 14

    Hougardy S, Nieberg T, Schneider J. BonnCell: automatic layout of leaf cells. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, 2013. 453–460

    Google Scholar 

  15. 15

    Ye W, Yu B, Ban Y-C, et al. Standard cell layout regularity and pin access optimization considering middle-of-line. In: Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh, 2015. 289–294

    Google Scholar 

  16. 16

    Xu X Q, Cline B, Yeric G, et al. A systematic framework for evaluating cell level middle-of-line (MOL) robustness for multiple patterning. Proc SPIE, 2015: 9427

    Google Scholar 

  17. 17

    Xu X Q, Cline B, Yeric G, et al. Self-aligned double patterning aware pin access and standard cell layout cooptimization. IEEE Trans Comput Aided Des Integr Circ Syst, 2015, 34: 699–712

    Article  Google Scholar 

  18. 18

    Hu S Y, Hu J. Pattern sensitive placement for manufacturability. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Austin, 2007. 27–34

    Google Scholar 

  19. 19

    Chen T C, Cho M, Pan D Z, et al. Metal-density-driven placement for CMP variation and routability. IEEE Trans Comput Aided Des Integr Circ Syst, 2008, 27: 2145–2155

    Article  Google Scholar 

  20. 20

    Shim S, Lee Y, Shin Y. Lithographic defect aware placement using compact standard cells without inter-cell margin. In: Proceedings of 19th Asia and South Pacific Design Automation Conference (ASPDAC), Singapore, 2014. 47–52

    Google Scholar 

  21. 21

    Gupta M, Jeong K, Kahng A B. Timing yield-aware color reassignment and detailed placement perturbation for bimodal cd distribution in double patterning lithography. IEEE Trans Comput Aided Des Integr Circ Syst, 2010, 29: 1229–1242

    Article  Google Scholar 

  22. 22

    Liebmann L, Pietromonaco D, Graf M. Decomposition-aware standard cell design flows to enable double-patterning technology. Proc SPIE, 2011: 7974

    Google Scholar 

  23. 23

    Agarwal K B, Alpert C J, Li Z, et al. Multi-patterning lithography aware cell placement in integrated circuit design, 2013. US Patent 8-495-548

    Google Scholar 

  24. 24

    Gao J-R, Yu B, Huang R, et al. Self-aligned double patterning friendly configuration for standard cell library considering placement. Proc SPIE, 2013: 8684

    Google Scholar 

  25. 25

    Tian H T, Du Y L, Zhang H B, et al. Triple patterning aware detailed placement with constrained pattern assignment. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2014. 116–123

    Google Scholar 

  26. 26

    Kuang J, Chow W-K, Young E F Y. Triple patterning lithography aware optimization for standard cell based design. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2014. 108–115

    Google Scholar 

  27. 27

    Lin T, Chu C. TPL-aware displacement-driven detailed placement refinement with coloring constraints. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Monterey, 2015. 75–80

    Google Scholar 

  28. 28

    Yu B, Xu X Q, Ga J-R, et al. Methodology for standard cell compliance and detailed placement for triple patterning lithography. IEEE Trans Comput Aided Des Integr Circ Syst, 2015, 34: 726–739

    Article  Google Scholar 

  29. 29

    Chien H-A, Chen Y-H, Han S-Y, et al. On refining row-based detailed placement for triple patterning lithography. IEEE Trans Comput Aided Des Integr Circ Syst, 2015, 34: 778–793

    Article  Google Scholar 

  30. 30

    Lin Y B, Yu B, Xu B Y, et al. Triple patterning aware detailed placement toward zero cross-row middle-of-line conflict. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, 2015. 396–403

    Google Scholar 

  31. 31

    Yu B, Xu X Q, Gao J-R, et al. Methodology for standard cell compliance and detailed placement for triple patterning lithography. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2013. 349–356

    Google Scholar 

  32. 32

    Lin Y B, Yu B, Zou Y, et al. Stitch aware detailed placement for multiple e-beam lithography. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Macao, 2016. 186–191

    Google Scholar 

  33. 33

    Liu C-Y, Chang Y-W. Simultaneous EUV flare-and CMP-aware placement. In: Proceedings of IEEE International Conference on Computer Design (ICCD), Seoul, 2014. 249–255

    Google Scholar 

  34. 34

    Shim S, Chung W, Shin Y. Defect probability of directed self-assembly lithography: fast identification and postplacement optimization. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, 2015. 404–409

    Google Scholar 

  35. 35

    Du Y L, Wong M D F. Optimization of standard cell based detailed placement for 16 nm FinFET process. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), Dresden, 2014. 357: 6

    Google Scholar 

  36. 36

    Fang S-Y, Liu I-J, Chang Y-W. Stitch-aware routing for multiple e-beam lithography. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), Austin, 2013. 25: 6

    Google Scholar 

  37. 37

    Cho M, Ban Y, Pan D Z. Double patterning technology friendly detailed routing. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2008. 506–511

    Google Scholar 

  38. 38

    Yuan K, Lu K, and Pan D Z. Double patterning lithography friendly detailed routing with redundant via consideration. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2009. 63–66

    Google Scholar 

  39. 39

    Lin Y-H, Li Y-L. Double patterning lithography aware gridless detailed routing with innovative conflict graph. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), Anaheim, 2010. 398–403

    Google Scholar 

  40. 40

    Lin Y-H, Ban Y-C, Pan D Z, et al. DOPPLER: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2011. 283–289

    Google Scholar 

  41. 41

    Ma Q, Zhang H B, Wong M D F. Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2012. 591–596

    Google Scholar 

  42. 42

    Lin Y-H, Yu B, Pan D Z, et al. TRIAD: a triple patterning lithography aware detailed router. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2012. 123–129

    Google Scholar 

  43. 43

    Hsu P-Y, Chang Y-W. Non-stitch triple patterning-aware routing based on conflict graph pre-coloring. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Chiba/Tokyo, 2015. 390–395

    Google Scholar 

  44. 44

    Liu Z Q, Liu C W, Young E F Y. An effective triple patterning aware grid-based detailed routing approach. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), Grenoble, 2015. 1641–1646

    Google Scholar 

  45. 45

    Gillijns W, Sherazi S M Y, Trivkovic D, et al. Impact of a SADP flow on the design and process for N10/N7 metal layers. Proc SPIE, 2015: 9427

    Google Scholar 

  46. 46

    Mirsaeedi M, Torres J A, Anis M. Self-aligned double-patterning (SADP) friendly detailed routing. Proc SPIE, 2011: 7974

    Google Scholar 

  47. 47

    Gao J-R, Pan D Z. Flexible self-aligned double patterning aware detailed routing with prescribed layout planning. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Napa Valley, 2012. 25–32

    Google Scholar 

  48. 48

    Kodama C, Ichikawa H, Nakayama K, et al. Self-aligned double and quadruple patterning-aware grid routing with hotspots control. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, 2013. 267–272

    Google Scholar 

  49. 49

    Du Y L, Ma Q, Song H, et al. Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), Austin, 2013. 93: 6

    Google Scholar 

  50. 50

    Liu I-J, Fang S-Y, Chang Y-W. Overlay-aware detailed routing for self-aligned double patterning lithography using the cut process. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2014. 50: 6

    Google Scholar 

  51. 51

    Fang S-Y. Cut mask optimization with wire planning in self-aligned multiple patterning full-chip routing. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Chiba/Tokyo, 2015. 396–401

    Google Scholar 

  52. 52

    Ding Y X, Chu C, Mak W-K. Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2015. 69: 6

    Google Scholar 

  53. 53

    Xu X Q, Yu B, Gao J-R, et al. PARR: pin access planning and regular routing for self-aligned double patterning. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2015. 28: 6

    Google Scholar 

  54. 54

    Yang J-S and Pan D Z. Overlay aware interconnect and timing variation modeling for double patterning technology. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2008. 488–493

    Google Scholar 

  55. 55

    van Oosten A, Nikolsky P, Huckabay J, et al. Pattern split rules! A feasibility study of rule based pitch decomposition for double patterning. Proc SPIE, 2007, 6730

    Google Scholar 

  56. 56

    Kahng A B, Park C-H, Xu X, et al. Layout decomposition approaches for double patterning lithography. IEEE Trans Comput Aided Des Integr Circ Syst, 2010, 29: 939–952

    Article  Google Scholar 

  57. 57

    Yuan K, Yang J-S, Pan D Z. Double patterning layout decomposition for simultaneous conflict and stitch minimization. IEEE Trans Comput Aided Des Integr Circ Syst, 2010, 29: 185–196

    Article  Google Scholar 

  58. 58

    Xu Y, Chu C. GREMA: graph reduction based efficient mask assignment for double patterning technology. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2009. 601–606

    Google Scholar 

  59. 59

    Xu Y, Chu C. A matching based decomposer for double patterning lithography. In: Proceedings of ACM International Symposium on Physical Design (ISPD), San Francisco, 2010. 121–126

    Google Scholar 

  60. 60

    Tang X P, Cho M. Optimal layout decomposition for double patterning technology. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2011. 9–13

    Google Scholar 

  61. 61

    Yang J-S, Lu K, Cho M, et al. A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Taipei, 2010. 637–644

    Google Scholar 

  62. 62

    Yu B, Yuan K, Ding D, et al. Layout decomposition for triple patterning lithography. IEEE Trans Comput Aided Des Integr Circ Syst, 2015, 34: 433–446

    Article  Google Scholar 

  63. 63

    Yu B, Yuan K, Zhang B Y, et al. Layout decomposition for triple patterning lithography. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2011. 1–8

    Google Scholar 

  64. 64

    Yu B, Pan D Z. Layout decomposition for quadruple patterning lithography and beyond. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2014. 53: 6

    Google Scholar 

  65. 65

    Fang S-Y, Chang Y-W, and Chen W-Y. A novel layout decomposition algorithm for triple patterning lithography. IEEE Trans Comput Aided Des Integr Circ Syst, 2014, 33: 397–408

    Article  Google Scholar 

  66. 66

    Kuang J, Young E F Y. An efficient layout decomposition approach for triple patterning lithography. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), Austin, 2013. 69: 6

    Google Scholar 

  67. 67

    Zhang Y, Luk W-S, Zhou H, et al. Layout decomposition with pairwise coloring for multiple patterning lithography. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2013. 170–177

    Google Scholar 

  68. 68

    Tian H T, Zhang H B, Ma Q, et al. A polynomial time triple patterning algorithm for cell based row-structure layout. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2012. 57–64

    Google Scholar 

  69. 69

    Tian H T, Du Y L, Zhang H B, et al. Constrained pattern assignment for standard cell based triple patterning lithography. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2013. 178–185

    Google Scholar 

  70. 70

    Tian H T, Zhang H B, Xiao Z G, et al. An efficient linear time triple patterning solver. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Chiba/Tokyo, 2015. 208–213

    Google Scholar 

  71. 71

    Chien H-A, Han S-Y, Chen Y-H, et al. A cell-based row-structure layout decomposer for triple patterning lithography. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Monterey, 2015. 67–74

    Google Scholar 

  72. 72

    Mirsaeedi M, Torres J A, Anis M. Self-aligned double patterning (SADP) layout decomposition. In: Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, 2011. 1–7

    Google Scholar 

  73. 73

    Zhang H B, Du Y L, Wong M D, et al. Self-aligned double patterning decomposition for overlay minimization and hot spot detection. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Diego, 2011. 71–76

    Google Scholar 

  74. 74

    Ban Y, Lucas K, Pan D Z. Flexible 2D layout decomposition framework for spacer-type double pattering lithography. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Diego, 2011. 789–794

    Google Scholar 

  75. 75

    Xiao Z G, Zhang H B, Du Y L, et al. A polynomial time exact algorithm for self-aligned double patterning layout decomposition. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Napa Valley, 2012. 17–24

    Google Scholar 

  76. 76

    Xiao Z G, Du Y L, Tian H T, et al. Optimally minimizing overlay violation in self-aligned double patterning decomposition for row-based standard cell layout in polynomial time. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2013. 32–39

    Google Scholar 

  77. 77

    Zhang H B, Du Y L, Wong M D F, et al. Characterization and decomposition of self-aligned quadruple patterning friendly layout. Proc SPIE, 2012: 8326

    Google Scholar 

  78. 78

    Kang W L, Feng C, Chen Y. Mask strategy and layout decomposition for self-aligned quadruple patterning. Proc SPIE, 2013: 8684

    Google Scholar 

  79. 79

    Ma Y S, Torres J A, Fenger G, et al. Challenges and opportunities in applying grapho-epitaxy DSA lithography to metal cut and contact/via applications. Proc SPIE, 2014: 9231

    Google Scholar 

  80. 80

    Ma Y S, Lei J J, Torres J A, et al. Directed self-assembly (DSA) grapho-epitaxy template generation with immersion lithography. Proc SPIE, 2015: 9423

    Google Scholar 

  81. 81

    Wong H-S P, Yi H, Tung M, et al. Physical layout design of directed self-assembly guiding alphabet for IC contact hole/via patterning. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Monterey, 2015. 65–66

    Google Scholar 

  82. 82

    Bita I, Yang J K W, Jung Y S, et al. Graphoepitaxy of self-assembled block copolymers on two-dimensional periodic patterned templates. Science, 2008, 321: 939–943

    Article  Google Scholar 

  83. 83

    Luo M, Epps T H. Directed block copolymer thin film self-assembly: emerging trends in nanopattern fabrication. Macromolecules, 2013, 46: 7567–7579

    Article  Google Scholar 

  84. 84

    Yi H, Bao X-Y, Zhang J, et al. Contact-hole patterning for random logic circuit using block copolymer directed self-assembly. Proc SPIE, 2012: 8323

    Google Scholar 

  85. 85

    Du Y L, Guo D F, Wong M D F, et al. Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2013. 186–193

    Google Scholar 

  86. 86

    Xiao Z G, Du Y L, Wong M D F, et al. DSA template mask determination and cut redistribution for advanced 1D gridded design. Proc SPIE, 2013: 8880

    Google Scholar 

  87. 87

    Ou J J, Yu B, Gao J-R, et al. Directed self-assembly based cut mask optimization for unidirectional design. In: Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh, 2015. 83–86

    Google Scholar 

  88. 88

    Fang S-Y, Hong Y-X, Lu Y-Z. Simultaneous guiding template optimization and redundant via insertion for directed self-assembly. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, 2015. 410–417

    Google Scholar 

  89. 89

    Mallik A, Ryckaert J, Mercha A, et al. Maintaining Moore’s law -enabling cost-friendly dimensional scaling. Proc SPIE, 2015: 9422

    Google Scholar 

  90. 90

    Badr Y, Torres A, Gupta P. Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7nm contacts/vias. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2015. 70: 6

    Google Scholar 

  91. 91

    Pain L, Jurdit M, Todeschini J, et al. Electron beam direct write lithography flexibility for ASIC manufacturing an opportunity for cost reduction. Proc SPIE, 2005, 5751

    Google Scholar 

  92. 92

    Kahng A B, Xu X, Zelikovsky A. Yield-and cost-driven fracturing for variable shaped-beam mask writing. Proc SPIE, 2004, 5567

    Google Scholar 

  93. 93

    Kahng A B, Xu X, Zelikovsky A. Fast yield-driven fracture for variable shaped-beam mask writing. Proc SPIE, 2006, 6283

    Google Scholar 

  94. 94

    Ma X, Jiang S L, Zakhor A. A cost-driven fracture heuristics to minimize sliver length. Proc SPIE, 2011: 7973

    Google Scholar 

  95. 95

    Sahouria E, Bowhill A. Generalization of shot definition for variable shaped e-beam machines for write time reduction. Proc SPIE, 2010: 7823

    Google Scholar 

  96. 96

    Elayat A, Lin T, Sahouria E, et al. Assessment and comparison of different approaches for mask write time reduction. Proc SPIE, 2011: 8166

    Google Scholar 

  97. 97

    Yuan K, Yu B, Pan D Z. E-Beam lithography stencil planning and optimization with overlapped characters. IEEE Trans Comput Aided Des Integr Circ Syst, 2012, 31: 167–179

    Article  Google Scholar 

  98. 98

    Edelsbrunner A, O’Rourke J, Welzl E. Stationing guards in rectilinear art galleries. Comput Vis Graph Image Process, 1984, 28: 167–176

    Article  Google Scholar 

  99. 99

    Lopez M A, Mehta D P. Efficient decomposition of polygons into L-shapes with application to VLSI layouts. ACM Trans Des Automat Electron Syst, 1996, 1: 371–395

    Article  Google Scholar 

  100. 100

    Yu B, Gao J-R, Pan D Z. L-Shape based layout fracturing for E-Beam lithography. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, 2013. 249–254

    Google Scholar 

  101. 101

    Kim J, Fan M. Hotspot detection on Post-OPC layout using full chip simulation based verification tool: A case study with aerial image simulation. Proc SPIE, 2003, 5256

    Google Scholar 

  102. 102

    Roseboom E, Rossman M, Chang F-C, et al. Automated full-chip hotspot detection and removal flow for interconnect layers of cell-based designs. Proc SPIE, 2007, 6521

    Google Scholar 

  103. 103

    Kahng A B, Park C-H, Xu X. Fast dual graph based hotspot detection. Proc SPIE, 2006, 6349

    Google Scholar 

  104. 104

    Yao H, Sinha S, Chiang C, et al. Efficient process-hotspot detection using range pattern matching. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2006. 625–632

    Google Scholar 

  105. 105

    Xu J Y, Sinha S, Chiang C C. Accurate detection for process-hotspots with vias and incomplete specification. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2007. 839–846

    Google Scholar 

  106. 106

    Yu Y-T, Chan Y-C, Sinha S, et al. Accurate process-hotspot detection using critical design rule extraction. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2012. 1167–1172

    Google Scholar 

  107. 107

    Wen W-Y, Li J-C, Lin S-Y, et al. A fuzzy-matching model with grid reduction for lithography hotspot detection. IEEE Trans Comput Aided Des Integr Circ Syst, 2014, 33: 1671–1680

    Article  Google Scholar 

  108. 108

    Ding D, Wu X, Ghosh J, et al. Machine learning based lithographic hotspot detection with critical-feature extraction and classification. In: Proceedings of IEEE International Conference on IC Design and Technology (ICICDT), Austin, 2009. 219–222

    Google Scholar 

  109. 109

    Drmanac D G, Liu F, Wang L-C. Predicting variability in nanoscale lithography processes. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2009. 545–550

    Google Scholar 

  110. 110

    Ding D, Torres J A, Pan D Z. High performance lithography hotspot detection with successively refined pattern identifications and machine learning. IEEE Trans Comput Aided Des Integr Circ Syst, 2011, 30: 1621–1634

    Article  Google Scholar 

  111. 111

    Wuu J-Y, Pikus F-G, Torres A, et al. Rapid layout pattern classification. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, 2011. 781–786

    Google Scholar 

  112. 112

    Ding D, Yu B, Ghosh J, et al. EPIC: efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Sydney, 2012. 263–270

    Google Scholar 

  113. 113

    Yu Y-T, Lin G-H, Jiang I H-R, et al. Machine-learning-based hotspot detection using topological classification and critical feature extraction. IEEE Trans Comput Aided Des Integr Circ Syst, 2015, 34: 460–470

    Article  Google Scholar 

  114. 114

    Yu B, Gao J-R, Ding D, et al. Accurate lithography hotspot detection based on principal component analysis-support vector machine classifier with hierarchical data clustering. J Micro/Nanolithogr MEMS MOEMS, 2015, 14: 011003

    Article  Google Scholar 

  115. 115

    Matsunawa T, Gao J-R, Yu B, et al. A new lithography hotspot detection framework based on AdaBoost classifier and simplified feature extraction. Proc SPIE, 2015: 9427

    Google Scholar 

  116. 116

    Kumar S V, Kim C H, Sapatnekar S. An analytical model for negative bias temperature instability. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2006. 493–496

    Google Scholar 

  117. 117

    Wang R S, Luo M L, Guo S F, et al. A unified approach for trap-aware device/circuit co-design in nanoscale CMOS technology. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington DC, 2013. 33.5.1–33.5.4

    Google Scholar 

  118. 118

    Roy S, Pan D Z. Reliability aware gate sizing combating NBTI and oxide breakdown. In: Proceedings of International Conference on VLSI Design, Mumbai, 2014. 38–43

    Google Scholar 

  119. 119

    Chakraborty A, Pan D Z. Skew management of NBTI impacted gated clock trees. In: Proceedings of ACM International Symposium on Physical Design (ISPD), San Francisco, 2010. 127–133

    Google Scholar 

  120. 120

    Roy S. Logic and Clock Network Optimization in Nanometer VLSI Circuits. Dissertation for the Doctoral Degree. The University of Texas at Austin, 2015

    Google Scholar 

  121. 121

    Kumar S V, Kim C H, Sapatnekar S S. NBTI aware synthesis of digital circuits. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Diego, 2007. 370–375

    Google Scholar 

  122. 122

    Yang X, Saluja K. Combating NBTI degradation via gate sizing. In: Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, 2007. 47–52

    Google Scholar 

  123. 123

    Vattikonda R, Wang W P, Cao Y. Modeling and minimization of PMOS NBTI effect for robust nanometer design. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2006. 1047–1052

    Google Scholar 

  124. 124

    Wu K-C, Marculescu D. Joint logic restructuring and pin reordering against NBTI-induced performance degradation. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), Nice, 2009. 75–80

    Google Scholar 

  125. 125

    Lin C-H, Roy S, Wang C-Y, et al. CSL: coordinated and scalable logic synthesis techniques for effective NBTI reduction. In: Proceedings of IEEE International Conference on Computer Design (ICCD), New York, 2015. 236–243

    Google Scholar 

  126. 126

    Lee K-T, Kang C Y, Yoo O S, et al. PBTI-associated high-temperature hot carrier degradation of nMOSFETs with metal-gate/high-k dielectrics. IEEE Electron Dev Lett, 2008. 389–391

    Google Scholar 

  127. 127

    Ebrahimi M, Oboril F, Kiamehr S, et al. Aging-aware logic synthesis. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2013. 61–68

    Google Scholar 

  128. 128

    Oboril F, Tahoori M B. ExtraTime: modeling and analysis of wearout due to transistor aging at microarchitecturelevel. In: Proceedings of IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Boston, 2012. 1–12

    Google Scholar 

  129. 129

    Fang J X, Sapatnekar S S. Scalable methods for the analysis and optimization of gate oxide breakdown. In: Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, 2010. 638–645

    Google Scholar 

  130. 130

    Aadithya K V, Demir A, Venugopalan S, et al. SAMURAI: an accurate method for modelling and simulating nonstationary random telegraph noise in SRAMs. In: Proceedings of IEEE/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), Grenoble, 2011. 1–6

    Google Scholar 

  131. 131

    Realov S, Shepard K L. Analysis of random telegraph noise in 45-nm CMOS using on-chip characterization system. IEEE Trans Electron Dev, 2013, 60: 1716–1722

    Article  Google Scholar 

  132. 132

    Grasser T, Kaczer B, Goes W, et al. The paradigm shift in understanding the bias temperature instability: from reaction–diffusion to switching oxide traps. IEEE Trans Electron Dev, 2011, 58: 3652–3666

    Article  Google Scholar 

  133. 133

    Wang R S, Huang R, Kim D-W, et al. New observations on the hot carrier and NBTI reliability of silicon nanowire transistors. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington DC, 2007. 821–824

    Google Scholar 

  134. 134

    Grasser T, Rott K, Reisinger H, et al. A unified perspective of RTN and BTI. In: Proceedings of IEEE International Reliability Physics Symposium (IRPS), Waikoloa, 2014. 4A.5.1–4A.5.7

    Google Scholar 

  135. 135

    Grasser T. Bias Temperature Instability for Devices and Circuits. New York: Springer Science & Business Media, 2013

    Google Scholar 

  136. 136

    Liu C Z, Zou J B, Wang R S, et al. Towards the systematic study of aging induced dynamic variability in nano-MOSFETs: adding the missing cycle-to-cycle variation effects into device-to-device variation. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington DC, 2011. 25.4.1–25.4.4

    Google Scholar 

  137. 137

    Liu C Z, Ren P P, Wang R S, et al. New observations on AC NBTI induced dynamic variability in scaled high-κ/metal-gate MOSFETs: characterization, origin of frequency dependence, and impacts on circuits. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2012. 19.5.1–19.5.4

    Google Scholar 

  138. 138

    Ren P P, Wang R S, Ji Z G, et al. New insights into the design for end-of-life variability of NBTI in scaled high-κ/metal-gate technology for the nano-reliability era. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2014. 34.1.1–34.1.4

    Google Scholar 

  139. 139

    Zou J B, Wang R S, Gong N B, et al. New insights into AC RTN in scaled high-k/metal-gate MOSFETs under digital circuit operations. In: Proceedings of Symposium on VLSI Technology (VLSIT), Honolulu, 2012. 139–140

    Google Scholar 

  140. 140

    Zou J B, Wang R S, Luo M L, et al. Deep understanding of AC RTN in MuGFETs through new characterization method and impacts on logic circuits. In: Proceedings of Symposium on VLSI Technology (VLSIT), Kyoto, 2013. T186–T187

    Google Scholar 

  141. 141

    Luo M, Wang R Q, Guo S N, et al. Impacts of random telegraph noise (RTN) on digital circuits. IEEE Trans Electron Dev, 2015, 62: 1725–1732

    Google Scholar 

  142. 142

    Ren P P, Xu X Q, Hao P, et al. Adding the missing time-dependent layout dependency into device-circuit-layout co-optimization: new findings on the layout dependent aging effects. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), Washington DC, 2015. 11.7.1–11.7.4

    Google Scholar 

  143. 143

    Wang T C, Hsieh T E, Wang M-T, et al. Stress migration and electromigration improvement for copper dual damascene interconnection. J Electrochem Soc, 2005, 152: G45–G49

    Article  Google Scholar 

  144. 144

    De Orio R L, Ceric H, Selberherr S. Physically based models of electromigration: from Black’s equation to modern TCAD models. Microelectron Reliab, 2010, 50: 775–789

    Article  Google Scholar 

  145. 145

    Sarychev M E, Zhitnikov Y V, Borucki L, et al. General model for mechanical stress evolution during electromigration. J Appl Phys, 1999, 86: 3068–3075

    Article  Google Scholar 

  146. 146

    Pak J, Lim S K, Pan D Z. Electromigration study for multiscale power/ground vias in TSV-based 3-D ICs. IEEE Trans Comput Aided Des Integr Circ Syst, 2014, 33: 1873–1885

    Article  Google Scholar 

  147. 147

    Gibson P, Hogan M, Sukharev V. Electromigration analysis of full-chip integrated circuits with hydrostatic stress. In: Proceedings of IEEE International Reliability Physics Symposium (IRPS), Waikoloa, 2014. IT.2.1–IT.2.7

    Google Scholar 

  148. 148

    Huang X, Yu T, Sukharev V, et al. Physics-based electromigration assessment for power grid networks. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2014. 80: 1–80: 6

    Google Scholar 

  149. 149

    Lienig J. Electromigration and its impact on physical design in future technologies. In: Proceedings of ACM International Symposium on Physical Design (ISPD), Stateline, 2013. 33–40

    Google Scholar 

  150. 150

    Pak J, Yu B, Pan D Z. Electromigration-aware redundant via insertion. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Chiba/Tokyo, 2015. 544–549

    Google Scholar 

  151. 151

    Posser G, Mishra V, Jain O, et al. A systematic approach for analyzing and optimizing cell-internal signal electromigration. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2014. 486–491

    Google Scholar 

  152. 152

    Xie J, Narayanan V, Xie Y. Mitigating electromigration of power supply networks using bidirectional current stress. In: Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), Salt Lake City, 2012. 299–302

    Google Scholar 

  153. 153

    Li D-A, Marek-Sadowska M, Nassif S R. A method for improving power grid resilience to electromigration-caused via failures. IEEE Trans Very Large Scale Integr Syst, 2015, 23: 118–130

    Article  Google Scholar 

  154. 154

    Pak J, Lim S K, Pan D Z. Electromigration-aware routing for 3D ICs with stress-aware EM modeling. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2012. 325–332

    Google Scholar 

  155. 155

    Chen X D, Liao C, Wei T Q, et al. An interconnect reliability-driven routing technique for electromigration failure avoidance. IEEE Trans Depend Secur Comput, 2012, 9: 770–776

    Article  Google Scholar 

  156. 156

    Jiang I H-R, Chang H-Y, Chang C-L. WiT: optimal wiring topology for electromigration avoidance. IEEE Trans Very Large Scale Integr Syst, 2012, 20: 581–592

    Article  Google Scholar 

  157. 157

    Nicolaidis M. Design for soft error mitigation. IEEE Trans Dev Mater Reliab, 2005, 5: 405–418

    Article  Google Scholar 

  158. 158

    Reviriengo P, Bleakly C J, Maestro J A. Structural dmr: a technique for implementation of soft-error-tolerant fir filters. IEEE Trans Circ Syst II, 2011, 58: 512–516

    Article  Google Scholar 

  159. 159

    Campbell K A, Vissa P, Pan D Z, et al. High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2015. 161: 6

    Google Scholar 

  160. 160

    Ebrahimi M, Liang C, Asadi H, et al. CLASS: combined logic and architectural soft error sensitivity analysis. In: Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, 2013. 601–607

    Google Scholar 

  161. 161

    Chou H-M, Hsiao M-Y, Chen Y-C, et al. Soft-error-tolerant design methodology for balancing performance, power, and reliability. IEEE Trans Very Large Scale Integr Syst, 2015, 23: 1628–1639

    Article  Google Scholar 

  162. 162

    Sheng W G, Xiao L Y, Mao Z G. Soft error optimization of standard cell circuits based on gate sizing and multiobjective genetic algorithm. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2009. 502–507

    Google Scholar 

  163. 163

    Cho H, Cher C-Y, Shepherd T, et al. Understanding soft errors in uncore components. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2015. 89: 6

    Google Scholar 

  164. 164

    Kiamehr S, Osiecki T, Tahoori M B, et al. Radiation-induced soft error analysis of SRAMs in SOI FinFET technology: a device to circuit approach. In: Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, 2014. 201: 6

    Google Scholar 

  165. 165

    Peng H-K, Wen C H-P, Bhadra J. On soft error rate analysis of scaled CMOS designs: a statistical perspective. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, 2009. 157–163

    Google Scholar 

  166. 166

    Cadence Virtuoso DFM. http://www.cadence.com

  167. 167

    Synopsys IC Validator. http://www.synopsys.com

  168. 168

    Calibre pattern matching. http://www.mentor.com/products

  169. 169

    Capodieci L. Beyond 28nm: new frontiers and innovations in design for manufacturability at the limits of the scaling roadmap. IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, 2012

    Google Scholar 

  170. 170

    Abercrombie D. Mastering the magic of multi-patterning. Mentor Graphics White Paper, 2013

    Google Scholar 

  171. 171

    Selim M. Circuit aging tools and reliability verification. In: MOS-AK Workshop, Grenoble, 2015

    Google Scholar 

  172. 172

    Tudor B, Wang J, Liu W D, et al. MOS device aging analysis with HSPICE and CustomSim. Synopsys White Paper, 2011

    Google Scholar 

  173. 173

    RedHawk-SEM. https://www.apache-da.com/products/redhawk/redhawk-sem

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Affiliations

  1. CSE Department, The Chinese University of Hong Kong, NT Hong Kong, China

    Bei Yu

  2. ECE Department, University of Texas at Austin, Austin, TX, 78712, USA

    Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou & David Z. Pan

  3. Cadence Design Systems, Inc., San Jose, CA, 95134, USA

    Subhendu Roy

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  1. Bei Yu
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  2. Xiaoqing Xu
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  3. Subhendu Roy
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  4. Yibo Lin
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  5. Jiaojiao Ou
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  6. David Z. Pan
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Correspondence to David Z. Pan.

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Yu, B., Xu, X., Roy, S. et al. Design for manufacturability and reliability in extreme-scaling VLSI. Sci. China Inf. Sci. 59, 061406 (2016). https://doi.org/10.1007/s11432-016-5560-6

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Keywords

  • design for manufacturability
  • design for reliability
  • VLSI CAD