A four-channel time-interleaved 30-GS/s 6-bit ADC in 0.18 μm SiGe BiCMOS technology

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  1. 1

    Pan H, Abidi A A. Signal folding in A/D converters. IEEE Trans Circ Syst-I, 2004, 51: 3–14

    Article  Google Scholar 

  2. 2

    Kull L, Toifl T, Schmatz M, et al. 90 Gs/s 8 bit 667 mW 64x interleaved SAR ADC in 32 nm digital SOI CMOS. In: Proceedings of IEEE International Solid- State Circuits Conference, San Francisco, 2014. 378–379

    Google Scholar 

  3. 3

    Wingender M, Chantier N, Nicolas S, et al. 12 Bit 1.5 GS/s L-Band ADC on 200 GHz SiGeC Technology. In: Proceedings of IEEE CIE International Conference on Radar, Chengdu, 2011. 265–268

    Google Scholar 

  4. 4

    Razavi B. Design consideration for interleaved ADCs. IEEE J Solid-State Circ, 2013, 48: 1806–1817

    Article  Google Scholar 

  5. 5

    Wu D Y, Jiang F, Zhou L, et al. A 4 GS/s 8 bit ADC fabricated in 0.35 μm SiGe BiCMOS technology. In: Proceedings of Bipolar/BiCMOS Circuits and Technology Meeting, Bordeaux, 2013. 69–72

    Google Scholar 

  6. 6

    Bouvier Y, Ouslimani A, Konczykowska A, et al. A1-GSample/s 15-GHz input bandwidth master-slave track-and-hold amplifier in InP DHBT technology. IEEE Trans Microw Theor Tech, 2009, 57: 3181–2009

    Article  Google Scholar 

  7. 7

    Lu Y, Kuo W L, Li X T, et al. An 8-bit, 12 GSample/sec SiGe track-and-hold amplifier. In: Proceedings of Bipolar/BiCMOS Circuits and Technology Meeting, Santa Barbara, 2005. 148–151

    Google Scholar 

  8. 8

    Singh U, Garg A, Raghavan B, et al. A 780 mW 4x 28 Gb/s transceiver for 100 GbE gearbox PHY in 40 nm CMOS. IEEE J Solid-State Circ, 2014, 49: 3116–3129

    Article  Google Scholar 

  9. 9

    Maloberti F. Date Converters. Berlin: Springer Press, 2007. 174–178

    Google Scholar 

Download references


This work was supported in part by National High Technology Research and Development Program of China (863 Program) (Grant No. 2013AA011201) and Wuhan Research Institute of Posts and Telecommunications (WRI). We would like to thank Dr. Jiang Fan from WRI for his technical support.

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Correspondence to Xinyu Liu.

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Zhu, X., Wu, D., Zhou, L. et al. A four-channel time-interleaved 30-GS/s 6-bit ADC in 0.18 μm SiGe BiCMOS technology. Sci. China Inf. Sci. 60, 129401 (2017). https://doi.org/10.1007/s11432-016-0711-y

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