Springer Nature is making SARS-CoV-2 and COVID-19 research free. View research | View latest news | Sign up for updates

Designs of low insertion loss optical router and reliable routing for 3D optical network-on-chip

三维光片上网络中低插入损耗光路由器和可靠性路由设计

  • 144 Accesses

  • 6 Citations

Abstract

Three-Dimensional Optical Network-on-Chip (3D ONoC) has recently emerged as a high-performance on-chip communication solution; however, owing to the intrinsic characteristics of photonic devices in existing 3D ONoC, the insertion loss caused by undesirable coupling among optical signals degrades network performance. Considering manufacturing defects and unpredictable noise sources that cause the failure of Optical Routers (ORs) in 3D ONoC, previous work simply abandoned the disabled OR when computing the restore path. In this paper, we propose a new OR structure that reduces insertion loss, and we present the design of a novel adaptive routing algorithm, FTRA-BL, based on the new OR structure with bidirectional waveguides, without abandoning any disabled ORs. Our FTRA-BL selects the normal waveguide in the disabled OR as the backup link so that the best macroscopic restore path can be guaranteed. Simulation results show that our method performs better than previous work in improving transmission reliability and latency.

摘要

创新点

  1. 1

    提出一种新的适合三维 Torus 拓扑的光路由器结构, 具有低插入损耗和高可扩展能力。

  2. 2.

    利用几何分析方法对网络中使用的光开关进行建模, 并利用传输矩阵分析光开关插入损耗。

  3. 3.

    提出适合光片上网络的可靠性路由策略, 并将故障粒度降低至光路由器内部, 提升了网络抗毁性能。

  4. 4.

    首次将单个波导双向传输策略引入到光片上网络中, 并提出双向链路的切换/控制机制。

This is a preview of subscription content, log in to check access.

References

  1. 1

    Chen Z, Gu H X, Yang Y T, et al. A hierarchical optical network-on-chip using central-controlled subnet and wavelength assignment. J Lightw Technol, 2014, 32: 930–938

  2. 2

    Ye Y Y, Xu J, Huang B H, et al. 3-D mesh-based optical network-on-chip for multiprocessor system-on-chip. IEEE Trans Comput Aided Des Integr Circ Syst, 2013, 32: 584–596

  3. 3

    Hou W G, Guo L, Cai Q, et al. 3D Torus ONoC: topology design, router modeling and adaptive routing algorithm. In: Proceedings of IEEE International Conference on Optical Communications and Networks, Suzhou, 2014. 1–4

  4. 4

    Chen K, Gu H X, Yang Y T, et al. A novel two-layer passive optical interconnection network for on-chip communication. J Lightwa Technol, 2014, 32: 1770–1776

  5. 5

    Koohi S, Hessabi S. All-optical wavelength-routed architecture for a power-efficient network on chip. IEEE Trans Comput, 2014, 63: 777–792

  6. 6

    Wu X W, Xu J, Ye Y Y, et al. An inter/intra-chip optical network for manycore processors. IEEE Trans VLSI Syst, 2015, 23: 678–691

  7. 7

    Nikdast M, Xu J, Duong L H K, et al. Fat-tree-based optical interconnection networks under crosstalk noise constrain. IEEE Trans VLSI Syst, 2015, 23: 156–169

  8. 8

    Nikdast M, Xu J, Duong L H K, et al. Crosstalk noise in WDM-based optical networks-on-chip: a formal study and comparison. IEEE Trans VLSI Syst, 2015, 23: 2552–2565

  9. 9

    Duong L H K, Nikdast M, Xu J, et al. Coherent crosstalk noise analyses in ring-based optical interconnects. In: Proceedings of 2015 Design, Automation & Test in Europe Conference & Exhibition, Grenoble, 2015. 9–13

  10. 10

    Hu T, Qiu C, Yu P, et al. Silicon photonic network-on-chip and enabling components. Sci China Technol Sci, 2013, 56: 543–553

  11. 11

    Micheli G D, Benini L. Nerworks on Chips: Technology and Tools. New York: Academic Press, 2006. 75–84

  12. 12

    Feng C C, Lu Z H, Jantsch A, et al. Addressing transient and permanent faults in NoC with efficient fault-tolerant deflection router. IEEE Trans VLSI Syst, 2013, 21: 1053–1066

  13. 13

    Ying H Y, Hofmann K, Hollstein T. Dynamic quadrant partitioning adaptive routing algorithm for irregular reduced vertical link density topology 3-dimensional network-on chips. In: Proceedings of IEEE International Conference on High Performance Computing & Simulation, Bologna, 2014. 516–522

  14. 14

    Jouybari H N, Mohammadi K. A low overhead, fault tolerant and congestion aware routing algorithm for 3D meshbased network-on-chips. Microprocessors Microsyst, 2014, 38: 991–999

  15. 15

    Ebrahimi M, Daneshtalab M, Plosila J, et al. MAFA: adaptive fault-tolerant routing algorithm for networks-on-chip. In: Proceedings of IEEE Euromicro Conference on Digital System Design, Izmir, 2012. 201–207

  16. 16

    Yariv A. Universal relations for coupling of optical power between microresonators and dielectric waveguides. Electron Lett, 2000, 36: 321–322

  17. 17

    Bogaerts W, De Heyn P, Van Vaerenbergh T, et al. Silicon microring resonators. Laser Photon Rev, 2012, 6: 47–73

  18. 18

    Chan J, Hendry G, Biberman A, et al. Architectural exploration of chip-scale photonic interconnection network designs using physical-layer analysis. J Lightw Technol, 2010, 28: 1305–1315

  19. 19

    Sherwood-Droz N, Wang H, Chen L, et al. Optical 4×4 hitless silicon router for optical networks-on-chip (NoC). Opt Expr, 2008, 16: 15915–15922

  20. 20

    Uenuma M, Motooka T. Temperature-independent silicon waveguide optical filter. Opt Lett, 2009, 34: 599–601

  21. 21

    Lan Y C, Lin H A, Lo S H, et al. A bidirectional NoC (BiNoC) architecture with dynamic self-reconfigurable channel. IEEE Trans Comput Aided Des Integr Circ Syst, 2011, 30: 427–440

  22. 22

    Zhu J Y, Qian Z L, Tsui C Y. BiLink: a high performance NoC router architecture using bi-directional link with double data rate. Integration VLSI J, 2016, 55: 30–42

  23. 23

    Guo P X, How W G, Guo L, et al. Reliable routing in 3D optical network-on-chip based on fault node reuse. In: Proceedings of IEEE International Workshop on Reliable Networks Design and Modeling, Munich, 2015. 92–98

  24. 24

    Pavlidis V F, Friedma E G. 3-D topologies for networks-on-chip. IEEE Trans VLSI Syst, 2007, 15: 1081–1090

Download references

Author information

Correspondence to Weigang Hou.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Guo, P., Hou, W. & Guo, L. Designs of low insertion loss optical router and reliable routing for 3D optical network-on-chip. Sci. China Inf. Sci. 59, 102302 (2016). https://doi.org/10.1007/s11432-016-0326-1

Download citation

Keywords

  • 3D ONoC
  • low insertion loss
  • reliable routing
  • bidirectional waveguide
  • low latency

关键词

  • 三维光片上网络
  • 低插入损耗
  • 可靠性路由
  • 双向波导
  • 低时延