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Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process

基于65纳米CMOS工艺的静态触发型电源钳位ESD保护电路设计

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Abstract

This work presents the design of a novel static-triggered power-rail electrostatic discharge (ESD) clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit (TC), the proposed circuit achieves the best ESD-conduction behavior while consuming the lowest leakage current (I leak) at the normal bias voltage among all investigated circuits in this work. In addition, the proposed circuit achieves an excellent false-triggering immunity against fast power-up pulses. All investigated circuits are fabricated in a 65-nm CMOS process. Performance superiorities of the proposed circuit are fully verified by both simulation and test results. Moreover, the proposed circuit offers an efficient on-chip ESD protection scheme considering the worst discharge case in the utilized process.

创新点

基于静态探测机制相对于瞬态探测机制在瞬态噪声性能上的优势, 本文提出了一种新型的静态触发型电源钳位ESD保护电路。通过有效的触发电路设计, 本文提出的新型保护电路能在ESD情况下相对于传统静态触发电路实现最好的泄放性能, 同时, 在正常操作情况下消耗最小的泄漏电流。本文提出的电路在65纳米CMOS工艺下得到了验证, 测试结果表明:本文提出的电路对与ESD事件一样快速的瞬态噪声具有免疫力, 同时, 本文提出的电路能为65纳米的CMOS工艺提供有效的片上ESD防护方案。

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Correspondence to Yuan Wang.

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Lu, G., Wang, Y., Zhang, L. et al. Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process. Sci. China Inf. Sci. 59, 122401 (2016). https://doi.org/10.1007/s11432-015-5455-y

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Keywords

  • electrostatic discharge (ESD)
  • power-rail ESD clamp circuit
  • detection mechanism
  • transient-noise immunity
  • false triggering
  • transmission line pulsing (TLP) test

关键词

  • 静电放电
  • 电源钳位ESD保护电路
  • 探测机制
  • 瞬态噪声免疫力
  • 误触发
  • 传输线脉冲测试