LSB page refresh based retention error recovery scheme for MLC NAND Flash


NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell (MLC) technology. High retention error rate in highly program/erase (P/E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit (LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Comparing with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.

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  1. 1

    Choi S, Kim D, Choi S, et al. 19.2 A 93.4 mm2 64 GB MLC NAND-flash memory with 16 nm CMOS technology. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). San Francisco: IEEE, 2014. 328–329

    Google Scholar 

  2. 2

    Helm M, Park J K, Ghalam A, et al. 19.1 A 128 Gb MLC NAND-flash device using 16 nm planar cell. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). San Francisco: IEEE, 2014. 326–327

    Google Scholar 

  3. 3

    Koh Y. NAND flash scaling beyond 20 nm. In: IEEE International Memory Workshop, IMW’09. Monterey: IEEE, 2009. 1–3

    Google Scholar 

  4. 4

    Yoon J H, Tressler G A. Advanced flash technology status, scaling trends & implications to enterprise SSD technology enablement. In: Flash Memory Summit, Santa Clara, 2012

    Google Scholar 

  5. 5

    Kang D, Lee K, Seo S, et al. Generation dependence of retention characteristics in extremely scaled NAND flash memory. IEEE Electron Device Lett, 2013, 34: 1139–1141

    Article  Google Scholar 

  6. 6

    Ho K C, Fang P C, Li H P, et al. A 45 nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). San Francisco: IEEE, 2013. 222–223

    Google Scholar 

  7. 7

    Dong G, Xie N, Zhang T. Enabling NAND Flash memory use soft-decision error correction codes at minimal read latency overhead. IEEE Trans Circuits Syst I Regular Papers, 2013, 60: 2412–2421

    Article  Google Scholar 

  8. 8

    Tanakamaru S, Yanagihara Y, Takeuchi K. Over-10x-Extended-Lifetime 76%-Reduced-Error Solid-State Drives (SSDs) with Error-Prediction LDPC Architecture and Error-Recovery Scheme (Invited Talk). Technical Report Ieice Icd, 2012, 112: 23–28

    Google Scholar 

  9. 9

    Tanakamaru S, Yanagihara Y, Takeuchi K. Error-prediction LDPC and error-recovery schemes for highly reliable solid-state crives (SSDs). IEEE J Solid-State Circ, 2013, 48: 2920–2933

    Article  Google Scholar 

  10. 10

    Tanakamaru S, Doi M, Takeuchi K. Error-prediction analyses in 1X, 2X and 3X nm NAND flash memories for systemlevel reliability improvement of solid-state drives (SSDs). In: IEEE International Reliability Physics Symposium (IRPS). Anaheim: IEEE, 2013. 3B.3.1–3B.3.6

    Google Scholar 

  11. 11

    Ma H, Zou H, Pan L, et al. MLC nand flash retention error recovery scheme through word line program disturbance. In: International Symposium on Next-Generation Electronics (ISNE). Kwei-Shan: IEEE, 2014. 1–2

    Google Scholar 

  12. 12

    Micheloni R, Marelli A, Commodaro S. NAND overview: from memory to systems. In: Micheloni R, Crippa L, Marelli A, eds. Inside NAND Flash Memories. New York: Spinger, 2010. 19–53

    Google Scholar 

  13. 13

    JEDEC Solid State Technology Association. Stress-test-driven qualification of integrated circuits. JESD47G. 2010

  14. 14

    Olivo P, Ricco B, Sangiorgi E. High-field-induced voltage-dependent oxide charge. Appl Phys Lett, 1986, 48: 1135–1137

    Article  Google Scholar 

  15. 15

    Cappelletti P, Bez R, Cantarelli D, et al. Failure mechanisms of flash cell in program/erase cycling. In: International Electron Devices Meeting IEDM’94 Technical Digest. San Francisco: IEEE, 1994. 291–294

    Google Scholar 

  16. 16

    Cai Y, Haratsch E F, Mutlu O, et al. Error patterns in MLC NAND flash memory: measurement, characterization, and analysis. In: Design, Automation and Test in Europe Conference and Exhibition (DATE). Dresden: IEEE, 2012. 521–526

    Google Scholar 

  17. 17

    Dong G, Pan Y, Xie N, et al. Estimating information-theoretical nand flash memory storage capacity and its implication to memory system design space exploration. IEEE Trans Very Large Scale Integration Syst, 2012, 20: 1705–1714

    Article  Google Scholar 

  18. 18

    Satoh S, Hagiwara H, Tanzawa T, et al. A novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbance. In: International Electron Devices Meeting IEDM’97 Technical Digest. Washington: IEEE, 1997. 291–294

    Google Scholar 

  19. 19

    Lee D, Hur H, Choi D. Effects of floating-gate interference on NAND flash memory cell operation. IEEE Electron Device Lett, 2002, 23: 264–266

    Article  Google Scholar 

  20. 20

    Monzio Compagnoni C, Spinelli A S, Gusmeroli R, et al. Ultimate accuracy for the nand flash program algorithm due to the electron injection statistics. IEEE Trans Electron Devices, 2008, 55: 2695–2702

    Article  Google Scholar 

  21. 21

    Lee J D, Choi J H, Park D, et al. Data retention characteristics of sub-100 nm NAND flash memory cells. IEEE Electron Device Lett, 2004, 24: 748–750

    Google Scholar 

  22. 22

    Papadas C, Pananakakis G, Ghibaudo G, et al. Modeling of the intrinsic retention characteristics of FLOTOX EEPROM cells under elevated temperature conditions. IEEE Trans Electron Devices, 1995, 42: 678–682

    Article  Google Scholar 

  23. 23

    Choi Y J, Suh K D, Koh Y N, et al. A high speed programming scheme for multi-level NAND flash memory. In: IEEE Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, 1996. 170–171

    Google Scholar 

  24. 24

    Miki H, Osabe T, Tega N, et al. Quantitative analysis of random telegraph signals as fluctuations of threshold voltages in scaled flash memory cells. In: Proceedings of 45th Annual IEEE International Reliability physics symposium. Phoenix: IEEE, 2007. 29–35

    Google Scholar 

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Correspondence to Haozhi Ma.

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Ma, H., Liu, L., Pan, L. et al. LSB page refresh based retention error recovery scheme for MLC NAND Flash. Sci. China Inf. Sci. 59, 042408 (2016).

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  • NAND Flash
  • reliability
  • retention
  • refresh
  • data error recovery