In this paper, we first reconstruct a novel planar static contention-free single-phase-clocked flipflop (S2CFF) based on high-performance fin-type field-effect transistors (FinFETs) to achieve high speed and ultralow power consumption. Benefiting from better control of the conductive channel, the shorted-gate (SG-mode) FinFET flip-flop obtains a persistent reduction of 56.7% in average power consumption as well as a considerable improvement in timing performance at a typical 10% data switching activity, while the low-power (LP-mode) FinFET flip-flop promotes the power reduction to 61.8% without appreciable degradation in speed. However, through further analysis of the simulation results, we have revealed an unnecessary energy loss caused by the redundant leaps of internal nodes at the static input ‘0’, which has a noticeable negative impact on total power consumption at low data switching activity. In order to overcome this defect, a conditional precharge technique is introduced to control the charging path, and we demonstrate that the independent-gate (IG-mode) FinFET is the best option for the added control transistor. The verification results indicate that our optimization reduces the power consumption by more than 50% at low data switching activity with an acceptable area and setup time penalty compared with that of LP-mode FinFET flip-flop.
This is a preview of subscription content, access via your institution.
Buy single article
Instant access to the full article PDF.
Tax calculation will be finalised during checkout.
Chen K T, Fujita T, Hara H, et al. A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptivecoupling configuration in 40 nm CMOS. In: Proceedings of IEEE Internation Solid-State Circuits Conference, San Francisco, 2011. 338–340
Kawaguchi H, Sakurai T. A reduced clock-swing flip-flop (RCSFF) for 63% power reduction. IEEE J Solid-State Circ, 1998, 33: 807–811
Alioto M, Consoli E, Palumbo G. Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part II. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2011, 19: 737–750
Giacomotto C, Nedovic N, Oklobdzija V G. The effect of the system specification on the optimal selection of clocked storage elements. IEEE J Solid-State Circ, 2007, 42: 1392–1404
Furuta J, Hamanaka C, Kobayashi K, et al. A 65 nm bistable cross-coupled dual modular redundancy flip-flop capable of protecting soft errors on the c-element. In: Proceedings of VLSI Circuits Symposium, Honolulu, 2010. 123–144
Matush B I, Mozdzen T J, Clark L T, et al. Area-efficient temporally hardened by design flip-flop circuits. IEEE Trans Nucl Sci, 2010, 57: 3588–3595
Hwang Y T, Lin J F, Sheu M H. Low power pulse-triggered flip-flop design with conditional pulse enhancement scheme. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2012, 20: 361–366
Li X Y, Jia S, Liu L M, et al. A pulse-generator-free hybrid Latch based Flip-flop (PHLFF). IEICE Trans Electron, 2012, E95-C: 1125–1127
Kawai N, Takayama S, Masumi J, et al. A fully static topologically-compressed 21-transistor flip-flop with 75% power saving. In: Proceedings of IEEE Asian Solid-State Circuits Conference, Singapore, 2013. 117–120
Kim Y, Arbor A, Jung W Y, et al. A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications. In: Proceedings of IEEE International Solid-State Circuits Conference, San Francisco, 2014. 466–467
Choi Y K, Asano K, Lindert N, et al. Ultra-thin body SOI MOSFET for deep-sub-tenth micron era. In: Proceedings of IEEE International Electron Devices Meeting, Washington, 1999. 919–921
Kedzierski J, Nowak E, Kanarsky T, et al. Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2002. 247–250
Hisamoto D, Lee W C, Kedzierski J, et al. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans Electron Dev, 2000, 47: 2320–2325
King T J. FinFETs for nanoscale CMOS digital integrated circuits. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, San Jose, 2005. 207–210
Liao N, Cui X X, Liao K, et al. Low power adiabatic logic based on FinFETs. Sci China Inf Sci, 2014, 57: 022402(13)
Muttreja A, Agarwal N, Jha N K. CMOS logic design with independent-gate FinFETs. In: Proceedings of 25th International Conference on Computer Design, Lake Tahoe, 2007. 560–567
Nanoscale Integration and Modeling (NIMO) Group. Predictive Technology Model. http://ptm.asu.edu/
Trivedi V P, Fossum J G, Zhang W M. Threshold voltage and bulk inversion effects in nonclassical CMOS devices with undoped ultra-thin bodies. Solid State Electron, 2007, 51: 170–178
Ma K S, Cui X X, Liao K, et al. Key characterization factors of accurate power modeling for FinFET circuits. Sci China Inf Sci, 2015, 58: 022403(13)
Baccarin D, Esseni D, Alioto M. Mixed FBB/RBB: a novel low-leakage technique for FinFET forced stacks. IEEE Trans VLSI Syst, 2012, 20: 1467–1472
Liao K, Cui X X, Liao N, et al. Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs. Sci China Inf Sci, 2014, 57: 042408(13)
Baccarin D, Esseni D, Alioto M. A novel back-biasing low-leakage technique for FinFET forced stacks. In: Proceedings of 2011 IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, 2011. 2079–2082
Massimo A. Comparative evaluation of layout density in 3T, 4T, and MT FinFET standard cells. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2011, 19: 751–762
Cui X X, Ma K S, Liao K, et al. A Dynamic-adjusting threshold-voltage scheme for FinFETs low power designs. In: Proceedings of IEEE Int Symp on Circuits and Systems, Beijing, 2013. 129–132
About this article
Cite this article
Liao, K., Cui, X., Liao, N. et al. Ultralow-power high-speed flip-flop based on multimode FinFETs. Sci. China Inf. Sci. 59, 042404 (2016). https://doi.org/10.1007/s11432-015-5407-6
- multimode FinFET