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Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process

带误触发免疫力的节省版图面积型电源钳位静电放电保护电路

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Abstract

A novel, area-efficient transient power-rail electrostatic discharge (ESD) clamp circuit is proposed in this work. Current-mirror capacitors are used to reduce the layout area. Logic threshold voltages of inverters are modified to ensure a fully active on-state for the clamp device in ESD conditions. The proposed circuit reduces the layout area by about 56% compared with a circuit without current-mirror capacitors. Transmission line pulse (TLP) test results based on a 65-nm CMOS process demonstrate that the proposed circuit is an efficient on-chip ESD protection scheme for this process. In addition, the proposed circuit achieves a good immunity to mis-triggering with respect to fast power-up transitions.

摘要

创新点

本文提出一种新型电源钳位静电放电保护电路。 通过电流镜型电容的使用, 新型保护电路的版图面积得到 56%的节省。 通过对反相器的逻辑阈值电压的调节, 新型保护电路在静电事件下具有更长的泄放时间。 新型保护电路在 65 纳米的 CMOS 工艺下实现。 测试结果表明, 新型保护电路能为该 65 纳米的工艺提供有效的静电放电保护方案, 同时, 新型保护电路对上升时间大于 300 纳秒的快速上电脉冲免疫。

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Correspondence to Yuan Wang 王源.

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Wang, Y., Lu, G., Guo, H. et al. Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process. Sci. China Inf. Sci. 59, 042407 (2016). https://doi.org/10.1007/s11432-015-5398-3

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Keywords

  • electrostatic discharge (ESD)
  • power-rail clamp circuit
  • transmission line pulse (TLP)
  • current mirror
  • mis-triggering

关键词

  • 静电放电
  • 电源钳位保护电路
  • 瞬态传输线脉冲
  • 电流镜
  • 误触发