Dynamically reconfigurable architecture for symmetric ciphers


In this paper, a very large scale integration (VLSI) architecture for a reconfigurable cryptographic processor is presented. Several optimization methods have been introduced into the design process. The interconnection tree between rows (ICTR) method reduces the interconnection complexity and results in a small area overhead. The hierarchical context organization (HCO) scheme reduces the total context size and increases the dynamic configuration speed. Most symmetric ciphers, including AES, DES, SHACAL-1, SMS4, and ZUC, can be implemented using the proposed architecture. Experimental results show that the proposed architecture has obvious advantages over current state-of-the-art architectures reported in the literature in terms of performance, area efficiency (throughput/area) and energy efficiency (throughput/power).

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Correspondence to Leibo Liu.

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Wang, B., Liu, L. Dynamically reconfigurable architecture for symmetric ciphers. Sci. China Inf. Sci. 59, 042403 (2016). https://doi.org/10.1007/s11432-015-5381-z

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  • reconfigurable cryptographic architecture
  • symmetric cryptography
  • algorithm flexibility
  • performance
  • area efficiency
  • energy efficiency