Dynamically reconfigurable architecture for symmetric ciphers

Abstract

In this paper, a very large scale integration (VLSI) architecture for a reconfigurable cryptographic processor is presented. Several optimization methods have been introduced into the design process. The interconnection tree between rows (ICTR) method reduces the interconnection complexity and results in a small area overhead. The hierarchical context organization (HCO) scheme reduces the total context size and increases the dynamic configuration speed. Most symmetric ciphers, including AES, DES, SHACAL-1, SMS4, and ZUC, can be implemented using the proposed architecture. Experimental results show that the proposed architecture has obvious advantages over current state-of-the-art architectures reported in the literature in terms of performance, area efficiency (throughput/area) and energy efficiency (throughput/power).

This is a preview of subscription content, access via your institution.

References

  1. 1

    Stallings W. Network and Internetwork Security: Principles and Practice. Upper Saddle River: Prentice Hall, 2010

    Google Scholar 

  2. 2

    Hiertz G R, Denteneer D, Stibor L, et al. The IEEE 802.11 Universe. IEEE Commun Mag, 2010; 48: 62–70

    Article  Google Scholar 

  3. 3

    LAN/MAN Standards Committee. IEEE Std 802.3-2008. 2008

  4. 4

    O’Melia S, Elbirt A J. Enhancing the performance of symmetric-key cryptography via instruction set extensions. IEEE Trans Very Large Scale Integr Syst, 2010; 18: 1505–1518

    Article  Google Scholar 

  5. 5

    Bossuet L, Grand M, Gaspar L, et al. Architectures of flexible symmetric key crypto engines: a survey from hardware coprocessor to multi-crypto-processor system on chip. ACM Comput Surv, 2013, 45: 41

    Article  Google Scholar 

  6. 6

    Granado-Criado J M, Vega-Rodrguez M A, Snchez-Prez J M, et al. A new methodology to implement the AES algorithm using partial and dynamic reconfiguration. Integration, 2010; 43: 72–80

    Google Scholar 

  7. 7

    Taherkhani S, Ever E, Gemikonakli O. Implementation of non-pipelined and pipelined data encryption standard (DES) using Xilinx Virtex-6 FPGA technology. In: Proceedings of IEEE 10th International Conference on Computer and Information Technology (CIT), Bradford, 2010. 1257–1262

    Google Scholar 

  8. 8

    Wang L, Jing J W, Liu Z B, et al. Evaluating optimized implementations of stream cipher ZUC algorithm on FPGA. In: Proceedings of 13th International Conference on Information and Communications Security, Beijing, 2011. 202–215

    Google Scholar 

  9. 9

    Venugopal V, Shila D M. High throughput implementations of cryptography algorithms on GPU and FPGA. In: Proceedings of IEEE International Instrumentation and Measurement Technology Conference, Minneapolis, 2013. 723–727

    Google Scholar 

  10. 10

    Bulens P, Standaert F, Quisquater J, et al. Implementation of the AES-128 on Virtex-5 FPGAs. In: Proceedings of 1st International Conference on Cryptology in Africa, Casablanca, 2008. 16–26

    Google Scholar 

  11. 11

    Standaert F X, Piret G, Rouvroy G, et al. FPGA implementations of the ICEBERG block cipher. Integration, 2007; 40: 20–27

    Google Scholar 

  12. 12

    Yang H, Basutkar N, Xue P, et al. Software-defined DVT-T2 demodulator using scalable DSP processors. IEEE Trans Consum Electron, 2013; 59: 428–434

    Article  Google Scholar 

  13. 13

    Garcia A, Berekovic M, Aa T V. Mapping of the AES cryptographic algorithm on a coarse-grain reconfigurable array processor. In: Proceedings of International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Leuven, 2008. 245–250

    Google Scholar 

  14. 14

    Rossi D, Mucci C, Campi F, et al. Application space exploration of a heterogeneous run-time configurable digital signal processor. IEEE Trans Very Large Scale Integr Syst, 2013; 21: 193–205

    Article  Google Scholar 

  15. 15

    PACT, X. XPP-III processor overview. White Paper Version. 2006

    Google Scholar 

  16. 16

    Majzoub S, Diab H. MorphoSys reconfigurable hardware for cryptography: the twofish case. J Supercomput, 2012; 59: 22–41

    Article  Google Scholar 

  17. 17

    Mucci C, Vanzolini L, Campi F, et al. Interactive presentation: implementation of AES/Rijndael on a dynamically reconfigurable architecture. In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE), EDA Consortium, 2007. 355–360

    Google Scholar 

  18. 18

    Elbirt A J, Paar C. An instruction-level distributed processor for symmetric-key cryptography. IEEE Trans Parall Distr Syst, 2005; 16: 468–480

    Article  Google Scholar 

  19. 19

    Cong J, Xiao B J. MrFPGA: a novel FPGA architecture with memristor-based reconfiguration. In: Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), San Diego, 2011. 1–8

    Google Scholar 

  20. 20

    NIST. Advanced encryption standard (AES). 2001. http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf

  21. 21

    NIST-FIPS. Data Encryption Standard. Federal Information Processing Standards (FIPS) Publication. 1999. http://csrc.nist.gov/encryption/tkencryption.html

  22. 22

    Handsehuh H, Naccache D S. SHACAL. In: Proceedings of 1st Open NESSIE Workshop, 2000. 13–14. http://www. oscca.gov.cn/UpFile/200621016423197990.pdf

    Google Scholar 

  23. 23

    OSCCA (Office of State Commercial Cryptography Administration, China). The SMS4 Block Cipher. 2006. http://www.oscca.gov.cn/UpFile/200621016423197990.pdf

    Google Scholar 

  24. 24

    ETSI/SAGE Specification. Specification of the 3GPP Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3. Document 2: ZUC Specification. Version 1.5. 2011

  25. 25

    Todman T J, Constantinides G A, Wilton S J, et al. Reconfigurable Computing: architectures and design methods. IEE Proc-Comput Dig Tech, 2005; 152: 193–207

    Article  Google Scholar 

  26. 26

    Xilinx. Virtex-5 FPGA User Guide. 2009

  27. 27

    Gentry C, Halevi S, Smart N P. Fully homomorphic encryption with polylog overhead. In: Proceedings of 31st Annual International Conference on the Theory and Applications of Cryptographic Techniques, Cambridge, 2012. 465–482

    Google Scholar 

  28. 28

    Lambrechts A, Raghavan P, Jayapala M, et al. Interconnect exploration for energy versus performance tradeoffs for coarse grained reconfigurable architectures. IEEE Trans Very Large Scale Integr Syst, 2009; 17: 151–155

    Article  Google Scholar 

  29. 29

    PACT. White Paper of Video Decoding on XPP-III. 2006

    Google Scholar 

  30. 30

    Liu B, Baas B M. Parallel AES encryption engines for many-core processor arrays. IEEE Trans Comput, 2013; 3: 536–547

    MathSciNet  Article  Google Scholar 

  31. 31

    Xilinx. XPower Estimator User Guide. 2012

    Google Scholar 

Download references

Author information

Affiliations

Authors

Corresponding author

Correspondence to Leibo Liu.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Wang, B., Liu, L. Dynamically reconfigurable architecture for symmetric ciphers. Sci. China Inf. Sci. 59, 042403 (2016). https://doi.org/10.1007/s11432-015-5381-z

Download citation

Keywords

  • reconfigurable cryptographic architecture
  • symmetric cryptography
  • algorithm flexibility
  • performance
  • area efficiency
  • energy efficiency