Value locality based storage compression memory architecture for ECG sensor node


This paper proposes a value compression memory architecture for QRS detection in ultra-low-power ECG sensor nodes. Based on the exploration of value spatial locality in the most critical preprocessing stage of the ECG algorithm, a cost efficient compression strategy, which reorganizes several adjacent sample values into a base value with several displacements, is proposed. The displacements will be half or quarter scale quantifications; as a result, the storage size is reduced. The memory architecture saves memory space by storing compressed data with value spatial locality into a compressed memory section and by using a small, uncompressed memory section as backup to store the uncompressed data when a value spatial locality miss occurs. Furthermore, a low-power accession strategy is proposed to achieve low-power accession. An embodiment of the proposed memory architecture has been evaluated using the MIT/BIH database, the proposed memory architecture and a low-power accession strategy to achieve memory space savings of 32.5% and to achieve a 68.1% power reduction with a negligible performance reduction of 0.2%.

This is a preview of subscription content, access via your institution.


  1. 1

    Pop V, de Francisco R, Pflug H, et al. Human++: wireless autonomous sensor technology for body area networks. In: Proceedings of the 16th Asia and South Pacific Design Automation Conference, Pacifico Yokohama, 2011. 561–566

    Google Scholar 

  2. 2

    Liu X, Zheng Y, Phyu M W, et al. Power and area efficient wavelet-based on-chip ECG processor for WBAN. In: Proceedings of International Conference on Body Sensor Networks (BSN), Singapore, 2010. 124–130

    Google Scholar 

  3. 3

    Liu X, Zheng Y, Phyu M W, et al. Multiple functional ECG signal is processing for wearable applications of long-term cardiac monitoring. IEEE Trans Biomed Eng, 2011; 58: 380–389

    Article  Google Scholar 

  4. 4

    Kim H, Yazicioglu R F, Torfs T, et al. A low power ECG signal processor for ambulatory arrhythmia monitoring system. In: Proceedings of IEEE Symposium on VLSI Circuits (VLSIC), Honolulu, 2010. 19–20

    Google Scholar 

  5. 5

    Ieong C I, Mak P I, Lam C P, et al. A 0.83-QRS detection processor using quadratic spline wavelet transform for wireless ECG acquisition in 0.35-CMOS. IEEE Trans Biomed Circ Syst, 2012; 6: 586–595

    Article  Google Scholar 

  6. 6

    Liu X, Zhou J, Yang Y, et al. A 457-nW cognitive multi-functional ECG processor. In: Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, 2013. 141–144

    Google Scholar 

  7. 7

    Yazicioglu R F, Kim S, Torfs T, et al. A 30W analog signal processor ASIC for portable biopotential signal monitoring. IEEE J Solid-State Circ, 2011; 46: 209–223

    Article  Google Scholar 

  8. 8

    Kim H, Yazicioglu R F, Kim S, et al. A configurable and low-power mixed signal SoC for portable ECG monitoring applications. In: Proceedings of Symposium on VLSI Circuits (VLSIC), Kyoto, 2011. 142–143

    Google Scholar 

  9. 9

    Jeon D, Chen Y P, Lee Y, et al. An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis. In: Proceedings of IEEE Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, 2014. 416–417

    Google Scholar 

  10. 10

    Ashouei M, Hulzink J, Konijnenburg M, et al. A voltage-scalable biomedical signal processor running ECG using 13pJ/cycle at 1MHz and 0.4 V. In: Proceedings of IEEE Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, 2011. 332–334

    Google Scholar 

  11. 11

    Kim H, Choi S, Yoo H J. A low power 16-bit RISC with lossless compression accelerator for body sensor network system. In: Proceedings of Asian Solid-State Circuits Conference, Hangzhou, 2006. 207–210

    Google Scholar 

  12. 12

    Kwong J, Chandrakasan A P. An energy-efficient biomedical signal processing platform. IEEE J Solid-State Circ, 2011; 46: 1742–1753

    Article  Google Scholar 

  13. 13

    ATMEL. 8-bit Atmel Microcontroller with 128Kbytes in-System Programmable Flash Rev 2467XCAVRC06/11. 2011

  14. 14

    Texas Instruments. MSP430x2xx Family User’s Guide. 2013

  15. 15

    Boichat N, Atienza D, Khaled N. Wavelet-based ECG delineation on a wearable embedded sensor platform. In: Proceedings of 6th International Wearable and Implantable Body Sensor Networks, Berkeley, 2009. 256–261

    Google Scholar 

  16. 16

    Yseboodt L, De Nil M, Huisken J, et al. Design of 100 µW wireless sensor nodes for biomedical monitoring. J Signal Process Syst, 2009; 57: 107–119

    Article  Google Scholar 

  17. 17

    Mamaghanian H, Khaled N, Atienza D, et al. Compressed sensing for real-time energy-efficient ECG compression on wireless body sensor nodes. IEEE Trans Biomed Eng, 2011; 58: 2456–2466

    Article  Google Scholar 

  18. 18

    Polastre J, Szewczyk R, Culler D. Telos: enabling ultra-low power wireless research. In: Proceedings of 4th International Symposium on Information Processing in Sensor Networks, Los Angeles, 2005. 364–369

    Google Scholar 

  19. 19

    Lee K H, Verma N. A 1.2C0.55 V general-purpose biomedical processor with configurable machine-learning accelerators for high-order, patient-adaptive monitoring. In: Proceedings of European Solid State Circuits Conference, Bordeaux, 2012. 285–288

    Google Scholar 

  20. 20

    Ekanayake V, Kelly IV C, Manohar R. An ultra low-power processor for sensor networks. ACM SIGARCH Comput Architect News, 2004; 32: 27–36

    Article  Google Scholar 

  21. 21

    Duarte F, Hulzink J, Zhou J, et al. A 36µW heartbeat-detection processor for a wireless sensor node. ACM Trans Des Automat Electron Syst, 2011, 16: 51

    Article  Google Scholar 

  22. 22

    Nazhandali L, Minuth M, Zhai B, et al. A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution. In: Proceedings of International Conference on Compilers, Architectures and Synthesis for Embedded Systems, San Francisco, 2005. 249–256

    Google Scholar 

  23. 23

    Pan J, Tompkins W J. A real-time QRS detection algorithm. IEEE Trans Biomed Eng, 1985; 32: 230–236

    Article  Google Scholar 

  24. 24

    Torfs T, Yazicioglu R F, Kim S, et al. Ultra low power wireless ECG system with beat detection and real time impedance measurement. In: Proceedings of Biomedical Circuits and Systems Conference (BioCAS), Paphos, 2010. 33–36

    Google Scholar 

  25. 25

    Martnez J P, Almeida R, Olmos S, et al. A wavelet-based ECG delineator: evaluation on standard databases. IEEE Trans Biomed Eng, 2004; 51: 570–581

    Article  Google Scholar 

  26. 26

    Moody G B, Mark R G, Goldberger A L. PhysioNet: a web-based resource for the study of physiologic signals. IEEE Eng Med Biol Mag, 2001; 20: 70–75

    Article  Google Scholar 

  27. 27

    Teman A, Pergament L, Cohen O, et al. A 250 mV 8 kb 40 nm ultra-low power 9T supply feedback SRAM (SF-SRAM). IEEE J Solid-State Circ, 2011; 46: 2713–2726

    Article  Google Scholar 

  28. 28

    Lutkemeier S, Jungeblut T, Berge H K O, et al. A 65 nm 32 b subthreshold processor with 9T multi-Vt SRAM and adaptive supply voltage control. IEEE J Solid-State Circ, 2013; 48: 8–19

    Article  Google Scholar 

  29. 29

    Kücük G, Basaran C. Reducing energy consumption of wireless sensor networks through processor optimizations. J Comput, 2007; 2: 67–74

    Article  Google Scholar 

  30. 30

    Hanson S, Seok M, Lin Y S, et al. A low-voltage processor for sensing applications with picowatt standby mode. IEEE J Solid-State Circ, 2009; 44: 1145–1155

    Article  Google Scholar 

Download references

Author information



Corresponding author

Correspondence to Zhijian Chen.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Zhao, C., Chen, C., Chen, Z. et al. Value locality based storage compression memory architecture for ECG sensor node. Sci. China Inf. Sci. 59, 042401 (2016).

Download citation


  • ECG R peak detection
  • wavelet transform
  • memory compression
  • low power
  • memory architecture