Single event upset rate modeling for ultra-deep submicron complementary metal-oxide-semiconductor devices
- 59 Downloads
Based on the integral method of single event upset (SEU) rate and an improved charge collection model for ultra-deep submicron complementary metal-oxide-semiconductor (CMOS) devices, three methods of SEU rate calculation are verified and compared. The results show that the integral method and the figure of merit (FOM) methods are basically consistent at the ultra-deep submicron level. By proving the validity of the carrier collection model considering charge sharing, the applicability of two FOM methods is verified, and the trends of single-bit and multiple-bit upset rates for ultra-deep submicron CMOS are analyzed.
Keywordsultra-deep submicron complementary metal-oxide-semiconductor devices single event upset rates charge sharing
- 2.He Y B, Chen S M. Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology. Sci China Inf Sci, 2014, 57: 102405Google Scholar
- 9.Blum D R. Hardened by design approaches for mitigating transient faults in memory-based systems. Dissertation for the Doctoral Degree. Pullman: Washington State University, 2007Google Scholar
- 14.Warren K W, Wilkinson J D, Weller R A, et al. Predicting neutron induced soft error rates: evaluation of accelerated ground based test methods. In: Proceedings of IEEE International Reliability Physics Symposium, Phoenix, 2008. 473–477Google Scholar
- 21.Roche P, Gasiot G, Uznanski S, et al. A commercial 65nm CMOS technology for space applications: heavy ion, proton and gamma test results and modeling. In: Proceedings of European Conference on Radiation and Its Effects on Components and Systems, Bruges, 2009. 456–464Google Scholar