A yield-enhanced global optimization methodology for analog circuit based on extreme value theory


The challenge in variation-aware circuit optimization with consideration of yield is the trade-off between optimized performance, yield and optimization runtime. This paper presents a practical variationaware circuit global optimization framework named GOYE, which shows the advantages on performance, yield and runtime. It uses an approach called constraint violation elimination (CVE) in global search phase to prune initial starting points and uses the gradient-based method in local search to locate optimum. The worst-case analysis (WCA), which is necessary for variation-aware circuit optimization, is nested in the local optimization process. The efficiency is significantly improved by a novel method based on extreme value theory (EVT). Our EVT-based method is also the first one that allows users to control the target yield such that under-design or over-design can be avoided. A design example in TSMC 65 nm technology is illustrated in the paper where all performance achieves three-sigma yield with consideration of environmental and inter-die/intra-die process variations.

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  1. 1

    Naviasky E, Nizic M. Mixed-signal design challenges and requirements. http://www.cadence.com/rl/Resources/white papers/mixed signal challenges wp.pdf

  2. 2

    Jafari A, Zekri M, Sadri S, et al. Design of analog integrated circuits by using genetic algorithm. In: Proceedings of the 2nd International Conference on Computer Engineering and Applications (ICCEA), Bali Island, 2010. 1: 578–581

    Google Scholar 

  3. 3

    Sabat S L, Kumar K S, Udgata S K. Differential evolution and swarm intelligence techniques for analog circuit synthesis. In: Proceedings of World Congress on Nature & Biologically Inspired Computing, Coimbatore, 2009. 469–474

    Google Scholar 

  4. 4

    Razzaghpour M, Rusu A. Analog circuit optimization via a modified imperialist competitive algorithm. In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, 2011. 2273–2276

    Google Scholar 

  5. 5

    Kotti M, Benhala B, Fakhfakh M, et al. Comparison between PSO and ACO techniques for analog circuit performance optimization. In: Proceedings of International Conference on Microelectronics (ICM), Hammamet, 2011. 1–6

    Google Scholar 

  6. 6

    Yuan J, Farhat N, van der Spiegel J. GBOPCAD: a synthesis tool for high-performance gain-boosted opamp design. IEEE Trans Circ Syst I: Regular Papers, 2007, 52: 1535–1544

    Article  Google Scholar 

  7. 7

    Rutenbar R A. Simulated annealing algorithms: an overview. IEEE Circ Device Mag, 1989, 5: 19–26

    Article  Google Scholar 

  8. 8

    Barros M, Guilherme J, Horta N. Analog circuits optimization based on evolutionary computation techniques. Integr VLSI J, 2010, 43: 136–155

    Article  MATH  Google Scholar 

  9. 9

    Schenkel F, Pronath M, Zizala S, et al. Mismatch analysis and direct yield optimization by specwise linearization and feasibility-guided search. In: Proceedings of the 38th Annual Design Automation Conference. New York: ACM, 2001. 858–863

    Google Scholar 

  10. 10

    Schwencker R, Schenkel F, Pronath M, et al. Analog circuit sizing using adaptive worst-case parameter sets. In: Proceedings of Design, Automation and Test in Europe Conference and Exhibition, Paris, 2002. 581–585

    Google Scholar 

  11. 11

    Pehl M, Zwerger M, Graeb H. Variability-aware automated sizing of analog circuits considering discrete design parameters. In: Proceedings of the 13th International Symposium on Integrated Circuits (ISIC), Singapore, 2011. 12–14

    Google Scholar 

  12. 12

    Wang Z, Director S. An efficient yield optimization method using a two-step linear approximation of circuit performance. In: Proceedings of IEEE European Design and Test Conference, Paris, 1994. 567–571

    Google Scholar 

  13. 13

    Liu B, Fernandez F V, Gielen G E. Efficient and accurate statistical analog yield optimization and variation-aware circuit sizing based on computational intelligence techniques. IEEE Trans Comput Aided Design Integr Circ Syst, 2011, 30: 793–805

    Article  Google Scholar 

  14. 14

    McConaghy T, Gielen G. Globally reliable variation-aware sizing of analog integrated circuits via response surfaces and structural homotopy. IEEE Trans Comput Aided Design, 2009, 28: 1627–1640

    Article  Google Scholar 

  15. 15

    Afacan E, Berkol G, Pusane A E, et al. Adaptive sized quasi-Monte Carlo based yield aware analog circuit optimization tool. In: Proceedings of the 5th European Workshop on CMOS Variability (VARI), Palma de Mallorca, 2014. 1–6

    Google Scholar 

  16. 16

    Debyser G, Gielen G. Efficient analog circuit synthesis with simultaneous yield and robustness optimization. In: Proceedings of IEEE/ACM International Conference on Computer Aided Design. New York: ACM, 1998. 308–311

    Google Scholar 

  17. 17

    Mukherjee T, Carley L, Rutenbar R. Efficient handling of operating range and manufacturing line variations in analog cell synthesis. IEEE Trans Comput Aided Design Integr Circ Syst, 2000, 19: 825–839

    Article  Google Scholar 

  18. 18

    Dharchoudhury A, Kang S. Worst-case analysis and optimization of VLSI circuit performances. IEEE Trans Comput Aided Design Integr Circ Syst, 1995, 14: 481–492

    Article  Google Scholar 

  19. 19

    Li X, Gopalakrishnan P, Xu Y, et al. Robust analog/RF circuit design with projection-based performance modeling. IEEE Trans Comput Aided Design Integr Circ Syst, 2007, 26: 2–15

    Article  Google Scholar 

  20. 20

    Director S, Feldmann P, Krishna K. Statistical integrated circuit design. IEEE J Solid-State Circ, 1993, 28: 193–202

    Article  Google Scholar 

  21. 21

    Antreich K, Graeb H, Wieser C. Circuit analysis and optimization driven by worst-case distances. IEEE Trans Comput Aided Design Integr Circ Syst, 1994, 13: 57–71

    Article  Google Scholar 

  22. 22

    Qian L X, Zhou D, Wang S G, et al. Worst case analysis of linear analog circuit performance based on Kharitonov’s rectangle. In: Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Shanghai, 2010. 800–802

    Google Scholar 

  23. 23

    Hao Z, Tan X D, Shen R, et al. Performance bound analysis of analog circuits considering process variations. In: Proceedings of the 48th ACM/EDAC/IEEE Design Automation Conference (DAC). New York: ACM, 2011. 310–315

    Google Scholar 

  24. 24

    Liu X, Palma-Rodriguez A A, Rodriguez-Chavez S, et al. Performance bound and yield analysis for analog circuits under process variations. In: Proceedings of 18th Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, 2013. 761–766

    Google Scholar 

  25. 25

    Kuo P, Saibua S, Huang G, et al. An efficient method for evaluating analog circuit performance bounds under process variations. IEEE Trans Circ Syst-II, 2012, 59: 351–355

    Article  Google Scholar 

  26. 26

    Huang G, Qian L, Saibua S, et al. An efficient optimization based method to evaluate the DRV of SRAM cells. IEEE Trans Circ Syst I, 2013, 60: 1511–1520

    Google Scholar 

  27. 27

    Tiwary S K, Tiwary P K, Rutenbar R A. Generation of yield aware Pareto surfaces for hierarchical circuit design space exploration. In: Proceedings of the 43rd annual Design Automation Conference. New York: ACM, 2006. 31–36

    Google Scholar 

  28. 28

    Singhee A, Rutenbar R A. Why quasi-Monte Carlo is better than Monte Carlo or latin hypercube sampling for statistical circuit analysis. IEEE Trans Comput Aided Design Integr Circ Syst, 2010, 29: 1763–1776

    Article  Google Scholar 

  29. 29

    Wikipedia. Newton’s method. http://en.wikipedia.org/wiki/Newton’s method

  30. 30

    Schittkowski K. NLPQLP: a new Fortran implementation of a sequential quadratic programming algorithm for parallel computing. http://tomopt.com/docs/nlpqlp.pdf

  31. 31

    Stoer J. Foundations of recursive quadratic programming methods for solving nonlinear programs. In: Computational Mathematical Programming. Berlin: Springer, 1985. 15

    Google Scholar 

  32. 32

    Nocedal J, Wright S J. Numerical Optimization. 2nd ed. Berlin: Springer, 2006

    MATH  Google Scholar 

  33. 33

    Graeb H. Analog Design Centering and Sizing. Berlin: Springer, 2007

    Google Scholar 

  34. 34

    Afacan E, Berkol G, Baskaya F, et al. Sensitivity based methodologies for process variation aware analog IC optimization. In: Proceedings of the 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Grenoble, 2014. 1–4

    Google Scholar 

  35. 35

    Afacan E, Berkol G, Pusane A E, et al. Adaptive sized quasi-Monte Carlo based yield aware analog circuit optimization tool. In: Proceedings of the 5th European Workshop on CMOS Variability (VARI), Palma de Mallorca, 2014. 1–6

    Google Scholar 

  36. 36

    Kotz S, Nadarajah S. Extreme Value Distributions: Theory and Applications. London: Imperial College Press, 2000

    Book  MATH  Google Scholar 

  37. 37

    The Mathworks Inc. Generalized Extreme Value Distribution. http://www.mathworks.com/help/stats/generalizedextreme- value-distribution.html

  38. 38

    Evmorfopoulos N E, Stamoulis G I, Avaritsiotis J N. A Monte Carlo approach for maximum power estimation based on extreme value theory. IEEE Trans CAD, 2002, 21: 4

    Article  Google Scholar 

  39. 39

    Sheppard M. Fit all valid parametric probability distributions to data. http://www.mathworks.com/matlabcentral/fileexchange/34943-fit-all-valid-parametric-probability-distributions-to-data/content/allfitdist.m

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Li, M., Huang, G., Wu, X. et al. A yield-enhanced global optimization methodology for analog circuit based on extreme value theory. Sci. China Inf. Sci. 59, 082401 (2016). https://doi.org/10.1007/s11432-015-0471-4

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  • global optimization
  • yield enhancement
  • analog design automation
  • extreme value analysis (EVA)
  • sequential quadratic programming (SQP)
  • worst-case analysis