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Simulation study of N-hit SET variation in differential cascade voltage switch logical circuits

差分电路中N型晶体管单粒子瞬态效应分析

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Abstract

The advancement in the process leads to more concern about the Single Event (SE) sensitivity of the Differential Cascade Voltage Switch Logic (DCVSL) circuits. The simulation results indicate that the Single Event Transient (SET) generated at the DCVSL gate is much larger than that at the ordinary CMOS gate, and their SET variation is different. Based on charge collection, in this paper, the effective collection time theory is proposed to set forth the SET pulse generated at the DCVSL gate. Through 3D TCAD mixed-mode simulation in 65 nm twin-well bulk CMOS process, the effects on SET variation of device parameters such as well contact size and environment parameters such as voltage are investigated.

摘要

创新点

本文基于65nm双阱工艺, 对差分逻辑与普通逻辑单粒子瞬态(SET)响应进行了对照研究。 研究表明受交叉耦合结构的影响, 差分逻辑SET响应与普通逻辑有很大的差异。 为了有效阐释差分逻辑SET随器件因素和环境因素的变化规律, 本文提出了有效收集时间理论。 本文认为晶体管敏感区电荷收集的时间可分为受限收集时间、自由收集时间和残余收集时间; 其中受限收集时间和自由收集时间对SET脉冲宽度其决定性作用。 对于普通逻辑, 粒子入射能量较高时, 受限收集时间支配着SET脉冲宽度; 然而对于差分逻辑, 当脉冲反馈特性较强时, 自由收集时间对SET的贡献接近于受限收集时间。 因而在设计差分逻辑电路时, 有必要适当选择晶体管尺寸, 调节脉冲反馈特性, 从而有效抑制SET。

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Authors and Affiliations

  1. Micro-electronics and Microprocessor Institute, College of Computer Science, National University of Defense Technology, Changsha, 410073, China

    PengCheng Huang, JianJun Chen, ZhenYu Wu, ZhengFa Liang, ChunMei Hu, Bin Liang & BiWei Liu

  2. National Laboratory for Parallel and Distributed Processing, College of Computer Science, National University of Defense Technology, Changsha, 410073, China

    ShuMing Chen

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  1. PengCheng Huang
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Correspondence to ShuMing Chen.

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Huang, P., Chen, S., Chen, J. et al. Simulation study of N-hit SET variation in differential cascade voltage switch logical circuits. Sci. China Inf. Sci. 58, 1–9 (2015). https://doi.org/10.1007/s11432-014-5210-9

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