Skip to main content
SpringerLink
Log in

A novel intelligent verification platform based on a structured analysis model

  • Research Paper
  • Published:
Science China Information Sciences Aims and scope Submit manuscript

Abstract

An intelligent verification platform based on a structured analysis model is presented. Using an abstract model mechanism with specific signal interfaces for user callback, the unified structured analysis data, shared by the electronic system level design, functional verification, and performance evaluation, enables efficient management review, auto-generation of code, and modeling in the transaction level. We introduce the class tree, flow parameter diagram, structured flow chart, and event-driven finite state machine as structured analysis models. As a sand table to carry maps from different perspectives and levels via an engine, this highly reusable platform provides the mapping topology to search for unintended consequences and the graph theory for comprehensive coverage and smart test cases. Experimental results show that the engine generates efficient test sequences, with a sharp increase in coverage for the same vector count compared with a random test.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Hu Z Y, Zhao Y, Wang X A, et al. Theory and verification of operator design methodology. Sci China Inf Sci, 2012, 55: 480–490

    Article  Google Scholar 

  2. Gluska A, Libis L. Shortening the verification cycle with synthesizable abstract models. In: 46th ACM/IEEE Design Automation Conference, San Francisco, 2009. 454–459

  3. Saponara S, Fanucci L, Coppola M. Design and coverage-driven verification of a novel network-interface IP macrocell for network-on-chip interconnects. Microprocess Microsyst, 2011, 35: 579–592

    Article  Google Scholar 

  4. Naveh Y, Rimon M, Jaeger I, et al. Constraint-based random stimuli generation for hardware verification. AI Mag, 2007, 28: 13–30

    Google Scholar 

  5. Gharehbaghi A M, Yaran B H, Hessabi S, et al. An assertion-based verification methodology for system-level design. Comput Electron Eng, 2007, 33: 269–284

    Article  MATH  Google Scholar 

  6. Kong L, Wu W C, He Yong, et al. Design of SoC verification platform based on VMM methodology. In: IEEE 8th International Conference on ASIC, Changsha, 2009. 1272–1275

    Google Scholar 

  7. Feng Y, Chen L. Constructucting method of VIP and VMM based SoC verification environment. In: 2nd International Conference on Mechanic Automation and Control Engineering (MACE), Mongolia, 2011. 3965–3968

    Google Scholar 

  8. Yun Y N, Kim J B, Kim N D, et al. Beyond UVM for practical SoC verification. In: International SoC Design Conference (ISOCC), Jeju, 2011. 158–162

  9. Li H W, Min Y H, Li Z C. Clustering of behavioral phases in FSMs and its applications to VLSI test. Sci China Ser F-Inf Sci, 2002, 45: 462–478

    MathSciNet  Google Scholar 

  10. Habibi A, Tahar S. Design and verification of SystemC transaction-level models. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2006, 14: 57–68

    Article  Google Scholar 

  11. Yu J S, Li T, Tan Q P. The use of UML sequence diagram for system-on-chip system level transaction-based functional verification. In: The 6th World Congress on Intelligent Control and Automation, Dalian, 2006. 6173–6177

    Google Scholar 

  12. Suhaib S, Mathaikutty D, Shukla S. System level design methodology for system on chips using multi-threaded graphs. In: IEEE International SOC Conference, Herndon, 2005. 133–136

    Google Scholar 

  13. Rimon M, Lichtenstein Y, Adir A, et al. Addressing test generation challenges for configurable processor verification. In: 11th Annual IEEE International High-Level Design Validation and Test Workshop, Monterey, 2006. 95–101

    Chapter  Google Scholar 

  14. Sun Z, Wang Y. A high efficient method to generate the verification vector of ICs (in Chinese). Acta Sci Natur Univ Pekinensis, 2007, 43: 92–95

    Google Scholar 

  15. Janick B, Eduard C, Alan H, et al. Verification Methodology Manual for SystemVerilog. New York: Springer, 2006. 105

    Google Scholar 

  16. Jenihhin M, Raik J, Chepurov A, et al. High-level decision diagrams based coverage metrics for verification and test. In: 10th Latin American Test Workshop (LATW), Rio de Janeiro, 2009. 1–6

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Key Laboratory of Integrated Micro-system Science and Engineering Applications, Peking University Shenzhen Graduate School, Shenzhen, 518055, China

    Zheng Xie, XinAn Wang, ZhiBin Lian & YongGui Luo

  2. EDA Center of Chinese Academy of Sciences, Beijing, 100029, China

    ZiYi Hu

Authors
  1. Zheng Xie
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. XinAn Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. ZhiBin Lian
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. YongGui Luo
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. ZiYi Hu
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to XinAn Wang.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Xie, Z., Wang, X., Lian, Z. et al. A novel intelligent verification platform based on a structured analysis model. Sci. China Inf. Sci. 56, 1–14 (2013). https://doi.org/10.1007/s11432-013-4817-6

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11432-013-4817-6

Keywords

Search

Navigation