Abstract
High-yield performance-efficient remapping architecture, repairing algorithms and redundancy analysis (HYPERA) are proposed for 2D memory. The proposed hypercube-based memory repair architecture consists of spare row-like subcubes with a modified ternary CAM with an address concentrator and a parallel sorter-like address concentrator. Generally, for an acceptable repair rate about 3% of spare subcubes and no more than 5% of hardware overhead are required. A modified Quine-McCluskey algorithm and the Essential Cube Pivoting algorithm are also developed for redundancy analysis. Almost 100% of repair rate can be obtained using only 32 equivalent rows under reasonable situations. Under less spare memory the repair rates of proposed approaches can be much higher than most results of previous work.
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Allan A, Barth R, Bennett H, et al. Test and test equipment. In: Technology Roadmap for Semiconductors—Executive Summary. 2009
Zorian Y, Shoukourian S. Embedded-memory test and repair: infrastructure IP for SoC yield. IEEE Des Test Comput, 2003, 20: 58–66
Huang C T, Wu C F, Li J F, et al. Built-in redundancy analysis for memory yield improvement. IEEE Trans Reliab, 2003, 52: 386–399
Wang L T, Wu C W, Wen X. VLSI Test Principles and Architectures. New York: Elsevier, 2006
Mazumder P, Jih Y S. A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits. IEEE Trans CAD Integr Circ Syst, 1993, 12: 24–36
Kawagoe T, Ohtani J, Niiro M, et al. A built-in self-repair analyzer (CRESTA) for embedded DRAMs. In: Proceedings of IEEE International Test Conference, Atlantic City, USA, 2000. 567–574
Jeong W, Han T, Kang S. An advanced BIRA using parallel sub-analyzers for embedded memories. In: Proceedings of IEEE International SoC Design Conference, Busan, Republic of Korea, 2009. 249–252
Hamdioui S, van de Goor A J. Efficient tests for realistic faults in dual-port SRAMs. IEEE Trans Comput, 2002, 51: 460–473
Shen Y N, Park N, Lombardi F. Spare cutting approaches for repairing memories. In: Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, Austin, Texas, USA, 1996. 106–111
Lu S K, Yang C L, Hsiao Y C, et al. Efficient BISR techniques for embedded memories considering cluster faults. IEEE Trans VLSI, 2010, 18: 184–193
Lee M, Wu C W. Method for Repairing Memory and System Thereof. ROC Patent, 200921690, 2009-05-16
Ohler P, Hellebrand S, Wunderlich H J. An integrated built-in test and repair approach for memories with 2D redundancy. In: Proceedings of 12th IEEE European Test Symposium, Convention Center, Freiburg, Germany, 2007. 91–96
Huang T C. Memory Address Remapping Architecture and Repairing Method Thereof. ROC Patent, 099141225, 2010-11-30
Huang T C, Lu K Y, Huang Y C. HYPERA: High-yield performance-efficient redundancy analysis. In: Proceedings of IEEE 19th Asian Test Symposium, Shanghai, China, 2010. 231–235
Malek M, Mourad A, Pandya M. Topological testing. In: Proceedings of International Test Conference, Washington DC, USA, 1989. 103–110
Park J H, Kim H C, Lim H S. Many-to-many disjoint path covers in hypercube-like interconnection networks with faulty elements. IEEE Trans Parallel Distr Syst, 2006, 17: 227–240
Bruck J, Ho C T. Fault-tolerant cube graphs and coding theory. IEEE Trans Inf Theory, 1996, 42: 2217–2221
Li S Y R. Unified algebraic theory of sorting, routing, multicasting, and concentration networks. IEEE Trans Commun, 2010, 58: 247–256
Batcher K E. Sorting networks and their applications. In: Proceedings of AFIPS Spring Joint Computer Conference, Atlantic City, USA, 1968. 307–314
Paterson M S. Improved sorting networks with O(logN) depth. Algorithmica, 1990, 5: 75–92
McCluskey J. Minimization of Boolean functions. J Bell Syst Tech, 1956, 35: 1417–1444
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Huang, TC. High-yield performance-efficient redundancy analysis for 2D memory. Sci. China Inf. Sci. 54, 1663–1676 (2011). https://doi.org/10.1007/s11432-011-4357-x
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DOI: https://doi.org/10.1007/s11432-011-4357-x