Abstract
A high-scale integrated optical receiver including a preamplifier, a limiting amplifier, a clock and data recovery (CDR) block, and a 1:4 demultiplexer (DEMUX) has been realized in a 0.25 μm CMOS technology. Using the loop parameter optimization method and the low-jitter circuit design technique, the rms and peak-to-peak jitter of the recovered 625 MHz clock are 9.4 and 46.3 ps, respectively, which meet the jitter specifications stipulated in ITU-T recommendation G.958. In response to 2.5 Gb/s PRBS input data (223−1), the recovered and frequency divided 625 MHz clock has a phase noise of −83.8 dBc/Hz at 20 kHz offset and the 2.5 Gb/s PRBS data has been demultiplexed into four 625 Mb/s data. The power dissipation is only 0.3 W under a single 3.3 V supply (excluding output buffers).
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Chen, Y., Wang, Z. & Zhang, L. A low-jitter low-power monolithically integrated optical receiver for SDH STM-16. Sci. China Inf. Sci. 54, 1293–1299 (2011). https://doi.org/10.1007/s11432-011-4218-7
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DOI: https://doi.org/10.1007/s11432-011-4218-7