Abstract
Concealing secret information in an image so that any perceptible evidence of the image alteration is insignificant, is known as image steganography. Image steganography can be implemented with either spatial or transform domain techniques. Spatial domain-based algorithms, generally the most widely used ones, refer to the process of embedding the secret information in the least significant bit positions of the cover image pixels. This paper proposes a chaotic tent map-based bit embedding as a novel steganography algorithm with a multicore implementation. The potential reasons for using chaotic maps in image steganography are sensitivity of these functions to initial conditions and control parameters. The computational complexity of the sequential least significant bit algorithm is known to be O(n). Hence, time complexity of the encryption/decryption algorithm is also a very important aspect. With the advantages offered by multicore processors, the proposed steganography algorithm can now be explicitly parallelized using the OpenMP API. As a pre-embedding operation, the quality of the randomness of the chaotic number sequences is tested with a NIST cryptographic test suite. The quality of the stego image is validated with statistical parameters such as structural similarity index (SSIM), mean square error (MSE) and peak signal-to-noise ratio (PSNR). Moreover, exploiting data parallelism inherent in the algorithm, multicore implementation of the algorithm with OpenMP API has also been reported. Proposed parallel version of the technique has been tested on five test samples of images for scalability analysis and results indicate significant speed up as compared to the sequential implementation of the technique.
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Gambhir, G., Mandal, J.K. Shared memory implementation and performance analysis of LSB steganography based on chaotic tent map. Innovations Syst Softw Eng 17, 333–342 (2021). https://doi.org/10.1007/s11334-021-00385-8
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DOI: https://doi.org/10.1007/s11334-021-00385-8