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From Statecharts to Verilog: a formal approach to hardware/software co-specification

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Abstract

Hardware/software co-specification is a critical phase in co-design. Our co-specification process starts with a high level graphical description in Statecharts and ends with an equivalent parallel composition of hardware and software descriptions in Verilog. In this paper, we first investigate the Statecharts formalism by providing it a formal syntax and a compositional operational semantics. Based on that, a semantics-preserving linking function is designed to compile specifications written in Statecharts into Verilog. The obtained Verilog specifications are then passed to a partitioning process to generate hardware and software subspecifications, where the correctness is guaranteed by algebraic laws of Verilog.

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Authors and Affiliations

  1. Department of Computer Science, Durham University, South Road, Durham, DH1 3LE, UK

    Shengchao Qin

  2. Department of Computer Science, National University of Singapore,  

    Wei-Ngan Chin

  3. Software Engineering Institute, East China Normal University, Shanghai, China

    Jifeng He

  4. School of Mathematical Sciences, Peking University, Beijing, China

    Zongyan Qiu

Authors
  1. Shengchao Qin
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  2. Wei-Ngan Chin
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  3. Jifeng He
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  4. Zongyan Qiu
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Corresponding author

Correspondence to Shengchao Qin.

Additional information

Part of the work appeared earlier in FME03 and ICFEM02. Wei-Ngan Chin is supported by Singapore Research Grant R-252-000-151-112. Jifeng He is supported by China 973 Project 2002CB312001. Zongyan Qiu is supported by NNSFC 60173003 and 60573081.

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Qin, S., Chin, WN., He, J. et al. From Statecharts to Verilog: a formal approach to hardware/software co-specification. Innovations Syst Softw Eng 2, 17–38 (2006). https://doi.org/10.1007/s11334-005-0020-2

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