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Implementation and Investigation of an Optimal Full Adder Design for Low Power and Reduced Delay Conditions

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Abstract

Full adder is one of the important components in electronics, used for various fundamental processing algorithms such as addition and multiplication. The application of these full adders is included in but not limited to Very Large-Scale Integration (VLSI) and Digital Signal Processing (DSP). To provide scalability and reliability to the advanced algorithms for high-end applications, the designing system of full adder should be enhanced. So, in this paper, we intended to improve the efficiency of a full adder circuit to work under low power and delay conditions. The software we used in this project is MENTOR GRAPHICS using 180 nm technology. The efficiency of the proposed transistor design is evaluated by analysing the power consumption, delay, PDP, capacitor load, delay w.r.t capacitance and PDP w.r.t capacitance. The parameters are compared between our proposed design and the literature schemes such as OLPFAD, DFEFA, DTLPCFA, and DPEHFA, respectively. It is evident that our proposed design outperforms the other.

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The data that support the findings of this study are available from the corresponding author, upon reasonable request.

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The code that is used this study are available from the corresponding author, upon reasonable request.

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The author(s) received no financial support for the research, authorship, and/or publication of this article.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India

    S. Arun Metha, B. Sai Tanuja, K. Preethi & N. P. N. S. Chandana

  2. Department of Electronics and Communication Engineering, Christ University, Bengaluru, Karnataka, India

    K. Praghash

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  1. K. Praghash
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  2. S. Arun Metha
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  3. B. Sai Tanuja
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  4. K. Preethi
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  5. N. P. N. S. Chandana
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Contributions

Conceptualization: K. Praghash; Methodology: S Arunmetha; Formal analysis and investigation: K. Praghash & S. Arunmetha; Writing-original draft preparation: S. Arunmetha & K. Praghash, Writing-review and editing: B. Sai Tanuja, K. Preethi, N. P. N. S. Chandana.

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Correspondence to K. Praghash.

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Praghash, K., Arun Metha, S., Sai Tanuja, B. et al. Implementation and Investigation of an Optimal Full Adder Design for Low Power and Reduced Delay Conditions. Wireless Pers Commun 126, 3041–3069 (2022). https://doi.org/10.1007/s11277-022-09851-3

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  • DOI: https://doi.org/10.1007/s11277-022-09851-3

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