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Hardware Implementation of Contention Resolution in a 4 × 4 Torus Network with Binary Optimized Routing Algorithm

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Abstract

In this paper, we propose and emulate a hardware model of a \(4\times 4\) torus topology with binary optimized routing algorithm. In Rsoft Inc. OptSim software, the hardware model for a node architecture and traffic model to resolve contention is simulated. The node architecture along with traffic scenario is implemented in the hardware test-bed and the routing scheme to resolve the contention is also verified.

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Acknowledgements

The corresponding author would like to place on record her deep appreciation and thanks to the Department of Science and Technology, SERB, Government of India, for the financial grant in the form of Young Scientist Scheme (YSS/2015/000986).

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  1. School of Electronics Engineering, VIT University, Chennai, Tamilnadu, India

    Abhilasha Sharma & R. G. Sangeetha

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  1. Abhilasha Sharma
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  2. R. G. Sangeetha
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Correspondence to R. G. Sangeetha.

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Sharma, A., Sangeetha, R.G. Hardware Implementation of Contention Resolution in a 4 × 4 Torus Network with Binary Optimized Routing Algorithm. Wireless Pers Commun 120, 1863–1872 (2021). https://doi.org/10.1007/s11277-021-08540-x

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