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Hardware Efficient Architectural Design for Physical Layer Security in Wireless Communication

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Abstract

The Wireless communication technology is an integral part of our day to day life. Since it is developed, secured transmission, error rate, energy, speed and cost of execution are the major issues faced by present techniques. A Hardware Efficient Secure Channel Coding Scheme for Physical Layer Security (HESCC-PLS) is designed to be incorporated and use a method named Extended Difference Family (EDF) Semi-Cyclic Low-Density Parity-Check (SC LDPC) code. The system architecture of the cryptochannel coder includes the design of several matrices for parity control, generator, scrambler, key stream generator and key based permutation. The cryptosystem is designed in such a manner that for each message block, the intentional error vector and the encryption are different so that the proposed architecture is safe from all typical attacks. The proposed system achieves a very high-performance ratio with minimum bit error rate.

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Authors and Affiliations

  1. Department of ECE, Sri Eshwar College of Engineering, Coimbatore, Tamil Nadu, India

    R. Pradeep

  2. Centre For Interdisciplinary Research, Karpagam Academy of Higher Education, Coimbatore, Tamil Nadu, India

    R. Kanimozhi

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  1. R. Pradeep
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  2. R. Kanimozhi
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Correspondence to R. Pradeep.

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Pradeep, R., Kanimozhi, R. Hardware Efficient Architectural Design for Physical Layer Security in Wireless Communication. Wireless Pers Commun 120, 1821–1836 (2021). https://doi.org/10.1007/s11277-021-08536-7

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  • DOI: https://doi.org/10.1007/s11277-021-08536-7

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