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Design and Analysis of (5, 10) Regular LDPC Encoder Using MRP Technique

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Abstract

An efficient compact encoding process with the pipelining design of Low Density Parity Check (LDPC) Encoder with a two stage, three stage and Maximal Rate Pipelining (MRP) structures are proposed in this work. Comparatively, LDPC encoding is more complex than decoding. The complexity mainly referred to the mathematical computation involved in the design of LDPC encoder. There are several methods used to design reduced parity check matrix, one of the methods involved is the Gauss Elimination method. Conventional and wave pipelining techniques are implemented to overcome the disadvantages of the area, latency, etc., The designed architectures are synthesized in SYNOPSYS tool and implemented in the XC3S-250E FPGA device. The overheads like power and area are efficiently reduced by wave pipelining and their efficiency can be proved by synthesis report. This showcases that the LDPC Encoders require less memory by using MRP structure.

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Authors and Affiliations

  1. Department of ECE, Sri Krishna College of Engineering and Technology, Coimbatore, India

    V. Nandalal

  2. Department of ECE, Sri Eshwar College of Engineering, Coimbatore, India

    V. Anand Kumar

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  1. V. Nandalal
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  2. V. Anand Kumar
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Nandalal, V., Anand Kumar, V. Design and Analysis of (5, 10) Regular LDPC Encoder Using MRP Technique. Wireless Pers Commun 118, 1295–1311 (2021). https://doi.org/10.1007/s11277-021-08075-1

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