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A Hardware Implementation for a New Post-correlation Anti-jamming Method

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Abstract

This paper describes the design and development of field programmable gate arrays based anti-jamming hardware. The key function of the system involves a new post-correlation filtering system to provide an anti-jamming feature in GPS receivers. The proper filter is applied to the values of the cross-ambiguity function in the search space, which decreases interference signal contribution without any need for prior knowledge of its specific characteristics. The structure is implemented and evaluated on the Xilinx ZedBoard which uses an XC7Z020 chip as the main processing unit. The design of the proposed filter structure is fully pipelined. It can be easily integrated with the acquisition system. By using this method, the receiver is capable of acquiring four satellites and successfully positioning in the presence of continuous wave interference with JSR up to 50 dB. The resource usage of the design is independent of the correlation output size. This can reduce the number of resources used and the computational burden greatly.

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Authors and Affiliations

  1. Department of Electrical Engineering, Iran University of Science and Technology, Narmak, Tehran, 16846-13114, Iran

    M. Aghadadashfam, A. Ramezani & M. R. Mosavi

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  1. M. Aghadadashfam
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  2. A. Ramezani
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  3. M. R. Mosavi
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Correspondence to M. R. Mosavi.

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Aghadadashfam, M., Ramezani, A. & Mosavi, M.R. A Hardware Implementation for a New Post-correlation Anti-jamming Method. Wireless Pers Commun 117, 2555–2574 (2021). https://doi.org/10.1007/s11277-020-07994-9

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