Abstract
FIR Filter always remains in linear phase with the help of symmetric coefficient. This feature makes it ideal for phase-sensitive applications like data communications. Design of FIR filter with energy efficiency makes excellent sense to achieve energy efficiency in digital selected frequency module of communication. We are using scaling of output load from 5000 to 0 pF to show an effect of output load on both on-chip and off-chip power consumption of FIR filter design. 20 nm technology based FVA1156 package and Kintex-7 family ultra-scale FPGA is taken under reconsideration for implementation of our model. With the use of HSTL_II IO standards, there is 84.39 and 92.83% reduction in IOs power when we scale down capacitance from 5000 to 500 and 0 pF respectively. With the use of HSTL_I_18 IO standards, there is 72.48 and 80.13% reduction in total on-chip power when we scale down capacitance from 5000 to 500 and 0 pF respectively. Along with IOs power and total on-chip power, we have also analyzed Off-chip device power, junction temperature, thermal margin, and different dynamic power likes Signal power, logic power, and DSP power.
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References
UltraScale architecture and product data sheet: Overview. https://www.xilinx.com/support/documentation/data_sheets/ds890-ultrascale-overview.pdf. Accessed on 11 March 2017.
Pandey, B., Kumar, T., Das, T., Yadav, R., & Pandey, O. J. (2014). Capacitance scaling based energy efficient FIR filter for digital signal processing. In International conference on optimization, reliability, and information technology (ICROIT) (pp. 448–451). IEEE.
Bansal, M., Bansal, N., Saini, R., Kalra, L., Singh, P. M., Pandey, B., & Akbar Hussain, D. M. (2015). FPGA based low power ROM design using capacitance scaling. In Advanced materials research (Vol. 1082, pp. 471–474). Trans Tech Publications.
Kumar, T., Pandey, B., Mussavi, S. H. A., & Zaman, N. (2015). CTHS based energy efficient thermal aware image ALU design on FPGA. Wireless Personal Communications, 85(3), 671–696.
Singh, P. R., Pandey, B., Kumar, T., Das, T., & Pandey, O. J. (2014). Output load capacitance based low power implementation of UART on FPGA. In 2014 international conference on computer communication and informatics (ICCCI) (pp. 1–4). IEEE.
Das, T., Pandey, B., Rahman, M. A., Kumar, T., & Siddiquee, T. (2013). Capacitance and frequency scaling based energy efficient image inverter design on FPGA. In International conference on communication and computer vision (ICCCV) (pp. 1–5). IEEE.
Kaur, A., et al. (2015). Capacitance scaling based energy efficient and tera hertz design of malayalam unicode reader on FPGA. International Journal of u-and e-Service, Science, and Technology, 8(8), 151–158.
Pandey, B., Kumar, T., Das, T., & Islam, S. M. M. (2014). Thermal mechanics based energy efficient FIR filter for digital signal processing. Applied Mechanics & Materials, 612, 65.
Pandey, B., Das, B., Kaur, A., Kumar, T., Khan, A. M., Hussain, D. A., et al. (2017). Performance evaluation of fir filter after implementation on different FPGA and SOC and its utilization in communication and network. Wireless Personal Communications, 95(2), 375–389.
Kumar, T., Pandey, B., & Das, T. (2014). Voltage scaling based energy efficient FIR filter design on FPGA. International Journal of Current Engineering and Technology. Special Issue-3, 200–204.
Khurshid, B., & Mir, R. N. (2016). An efficient FIR filter structure based on technology-optimized multiply-adder unit targeting LUT-based FPGAs. Circuits, Systems, and Signal Processing, 36, 1–40.
Bhat, D., Kaur, A., & Singh, S. (2015). Wireless sensor network specific low power FIR filter design and implementation on FPGA. In 2015 2nd international conference on computing for sustainable global development (INDIACom) (pp. 1534–1536). IEEE.
Park, S. Y., & Meher, P. K. (2014). Efficient FPGA and ASIC realizations of a DA-based reconfigurable FIR digital filter. IEEE Transactions on Circuits and Systems II: Express Briefs, 61(7), 511–515.
Kalia, K., Nanda, K., Aggarwal, A., Goel, A., & Malhotra, S. (2015). I2C and HSTL IO standard based low power thermal aware adder design on 45 nm FPGA. Advanced Materials Research, 1098, 31–36.
Aikawa, N., Isomura, H., & Ishikawa, T. (1996). Design of finite impulse response transmitter and receiver filters for data communication system. Electronics and Communications in Japan (Part III: Fundamental Electronic Science), 79(11), 25–34.
Microwave and RF. http://www.mwrf.com/test-and-measurement/design-finite-impulse-response-digital-filters-1. Accessed on 22 June 2017.
Deshpande, R., Kumar, B., & Jain, S. B. (2010). Highly narrow rejection bandwidth finite impulse response notch filters for communication. IET Communications, 4(18), 2208–2216.
Rajatheva, N., & Shwedyk, E. (2000). Distance properties of finite-impulse response channels. IEEE Transactions on Communications, 48(9), 1429–1431.
Dynamic Power Consumption. http://www.siliconintelligence.com/people/binu/perception/node13.html. Accessed on 22 June 2017.
Thind, V., Pandey, B., Kalia, K., Das, T., & Kumar, T. (2016). FPGA based low power DES algorithm design and implementation using HTML technology. International Journal of Software Engineering and Its Application, 10, 81–92.
Saxena, A., Bhatt, A. K., Pandey, B., Tripathi, P., & Dutt, G. (2016). HSTL IO standards based processor specific green counter design on 90 nm FPGAAbhay Saxena. International Journal of Control and Automation, 9(7), 331–342.
Agrawal, T., Srivastava, V., & Kumar, A. (2015). Designing of power efficient ROM using LVTTL and mobile-DDR IO standard on 28 nm FPGA. In International conference on computational intelligence and communication networks (CICN) (pp. 1334–1337). IEEE.
Kaur, K., Ghuman, G. S., & Kaur, T. (2014). Design of high frequency and energy efficient 3D frame buffer on 40 nm FPGA. In 2014 international conference on computational intelligence and communication networks (CICN) (pp. 943–946). IEEE.
Verma, S., Gaba, D., & Pandey, B. (2015). HSUL based 802.11 WLAN channel specific energy efficient ALU design on FPGA. In 2015 2nd international conference on signal processing and integrated networks (SPIN) (pp. 860–864). IEEE.
Kalia K., et al. (2015). Pseudo open drain IO standards based energy efficient solar charge sensor design on 20 nm FPGA. In 2015 IEEE 11th international conference on power electronics and drive systems (PEDS) (pp. 367–372). IEEE.
Garg, D., Sohal, H., & Ahuja, S. (2016). SSTL IO standard based power efficient data processing device design on FPGA. In 2016 international conference on circuit, power and computing technologies (ICCPCT). IEEE.
UltraScale Architecture SelectIO Resources User Guide, UG571 (v1.6). https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf. Accessed on 25 October 2016.
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Pandey, B., Pandey, N., Kaur, A. et al. Scaling of Output Load in Energy Efficient FIR Filter for Green Communication on Ultra-Scale FPGA. Wireless Pers Commun 106, 1813–1826 (2019). https://doi.org/10.1007/s11277-018-5717-2
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DOI: https://doi.org/10.1007/s11277-018-5717-2