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Holding State Performance Amelioration by Exploitation of NMOS Body Effect in 1T DRAM Cells

Abstract

In this study curtailing of idle current in 1T1C and 1T1M DRAM cells by increasing threshold voltage during holding state is analyzed. This is attained by connecting the bulk to source in the active phases and pulling it below source potential throughout the holding phase. The proposed technique leads to body effect which affects the threshold voltage improving leakage current. The 1T1C and 1T1M discussed in this paper are volatile and non-volatile (memristor based) respectively. Memory design is fast becoming the pacemaker in the modern technology design which now requires DRAM cells with prolonged holding period and low idle power hence the need for lowering the leakage current. The dynamic nature of the 1T1C is due to charge leakage and the leakage current flowing through the 1T1M cell affects mem-resistance all this leading to state distortion. Idle current has of-late become one of the major contributors of power in large memory arrays in which in-active periods now dominates active period and by this technique idle power is reduced in both volatile and non-volatile cells. The proposed technique was implemented and simulations were done at different voltage levels at 45 nm technology. The method improved the leakage current, holding time and leakage power but at the expense of area and writing power.

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Abbreviations

1T1C:

One transistor one capacitor

1T1M:

One transistor one memristor

DRAM:

Dynamic random access memory

NMOS:

N-channel MOSFET

VDD :

Supply voltage (+ ve)

Pdyn :

Dynamic power

Vt :

Threshold voltage

Tpd :

Transistor propagation delay

fmax :

Maximum operating frequency

Ileak :

Leakage current

S:

Subthreshold slope

Pidle :

Idle power

Pave :

Average power

Pstatic biasing :

Static power

Vtno :

Threshold voltage @ zero bias

γ :

Coefficient of body effect

Vsb :

Voltage across and source and body

Vgs :

Gate-source voltage

Tox :

Oxide layer thickness

SiO2 :

Silicon dioxide

J:

Leakage current density

Vb :

Junction voltage

Io :

Current@Vgs = Vt

Isub :

Subthreshold current

M(q):

Memresistance

Pt :

Platinum nano-wire contacts

O2 :

Positively charged oxygen ion vacancies

RON :

ON-resistance

ROFF :

OFF resistance

VLSI:

Very large scale integration

L:

Length of TiO2 + TiO2−x

Wlt :

Width of the region

Vlt :

Voltage across the memristor device

frefresh :

Refreshing frequency

tn :

Holding time

B:

Ratio of the maximum R OFF to R ON

µv :

Dopant mobility

Vbias :

Biasing voltage

Vsb :

Source to body voltage

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Acknowledgement

The authors of this paper owe gratitude to ITM University Gwalior in Collaboration with Cadence Design System Bangalore for the support provided.

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Correspondence to Peter Bukelani Musiiwa.

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Musiiwa, P.B., Akashe, S. Holding State Performance Amelioration by Exploitation of NMOS Body Effect in 1T DRAM Cells. Wireless Pers Commun 99, 47–66 (2018). https://doi.org/10.1007/s11277-017-5036-z

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Keywords

  • Memristor
  • Capacitor
  • DRAM
  • Holding state
  • Performance
  • Amelioration