Holding State Performance Amelioration by Exploitation of NMOS Body Effect in 1T DRAM Cells

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Abstract

In this study curtailing of idle current in 1T1C and 1T1M DRAM cells by increasing threshold voltage during holding state is analyzed. This is attained by connecting the bulk to source in the active phases and pulling it below source potential throughout the holding phase. The proposed technique leads to body effect which affects the threshold voltage improving leakage current. The 1T1C and 1T1M discussed in this paper are volatile and non-volatile (memristor based) respectively. Memory design is fast becoming the pacemaker in the modern technology design which now requires DRAM cells with prolonged holding period and low idle power hence the need for lowering the leakage current. The dynamic nature of the 1T1C is due to charge leakage and the leakage current flowing through the 1T1M cell affects mem-resistance all this leading to state distortion. Idle current has of-late become one of the major contributors of power in large memory arrays in which in-active periods now dominates active period and by this technique idle power is reduced in both volatile and non-volatile cells. The proposed technique was implemented and simulations were done at different voltage levels at 45 nm technology. The method improved the leakage current, holding time and leakage power but at the expense of area and writing power.

Keywords

Memristor Capacitor DRAM Holding state Performance Amelioration 

List of Symbols

1T1C

One transistor one capacitor

1T1M

One transistor one memristor

DRAM

Dynamic random access memory

NMOS

N-channel MOSFET

VDD

Supply voltage (+ ve)

Pdyn

Dynamic power

Vt

Threshold voltage

Tpd

Transistor propagation delay

fmax

Maximum operating frequency

Ileak

Leakage current

S

Subthreshold slope

Pidle

Idle power

Pave

Average power

Pstatic biasing

Static power

Vtno

Threshold voltage @ zero bias

γ

Coefficient of body effect

Vsb

Voltage across and source and body

Vgs

Gate-source voltage

Tox

Oxide layer thickness

SiO2

Silicon dioxide

J

Leakage current density

Vb

Junction voltage

Io

Current@Vgs = Vt

Isub

Subthreshold current

M(q)

Memresistance

Pt

Platinum nano-wire contacts

O2

Positively charged oxygen ion vacancies

RON

ON-resistance

ROFF

OFF resistance

VLSI

Very large scale integration

L

Length of TiO2 + TiO2−x

Wlt

Width of the region

Vlt

Voltage across the memristor device

frefresh

Refreshing frequency

tn

Holding time

B

Ratio of the maximum ROFF to RON

µv

Dopant mobility

Vbias

Biasing voltage

Vsb

Source to body voltage

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Copyright information

© Springer Science+Business Media, LLC 2017

Authors and Affiliations

  1. 1.Department of Electronic EngineeringHarare Institute of TechnologyHarareZimbabwe
  2. 2.Department of Electronics and Communication EngineeringITM UniversityGwaliorIndia

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