Wireless Personal Communications

, Volume 99, Issue 1, pp 47–66 | Cite as

Holding State Performance Amelioration by Exploitation of NMOS Body Effect in 1T DRAM Cells

  • Peter Bukelani Musiiwa
  • Shyam Akashe


In this study curtailing of idle current in 1T1C and 1T1M DRAM cells by increasing threshold voltage during holding state is analyzed. This is attained by connecting the bulk to source in the active phases and pulling it below source potential throughout the holding phase. The proposed technique leads to body effect which affects the threshold voltage improving leakage current. The 1T1C and 1T1M discussed in this paper are volatile and non-volatile (memristor based) respectively. Memory design is fast becoming the pacemaker in the modern technology design which now requires DRAM cells with prolonged holding period and low idle power hence the need for lowering the leakage current. The dynamic nature of the 1T1C is due to charge leakage and the leakage current flowing through the 1T1M cell affects mem-resistance all this leading to state distortion. Idle current has of-late become one of the major contributors of power in large memory arrays in which in-active periods now dominates active period and by this technique idle power is reduced in both volatile and non-volatile cells. The proposed technique was implemented and simulations were done at different voltage levels at 45 nm technology. The method improved the leakage current, holding time and leakage power but at the expense of area and writing power.


Memristor Capacitor DRAM Holding state Performance Amelioration 

List of Symbols


One transistor one capacitor


One transistor one memristor


Dynamic random access memory


N-channel MOSFET


Supply voltage (+ ve)


Dynamic power


Threshold voltage


Transistor propagation delay


Maximum operating frequency


Leakage current


Subthreshold slope


Idle power


Average power

Pstatic biasing

Static power


Threshold voltage @ zero bias


Coefficient of body effect


Voltage across and source and body


Gate-source voltage


Oxide layer thickness


Silicon dioxide


Leakage current density


Junction voltage


Current@Vgs = Vt


Subthreshold current




Platinum nano-wire contacts


Positively charged oxygen ion vacancies




OFF resistance


Very large scale integration


Length of TiO2 + TiO2−x


Width of the region


Voltage across the memristor device


Refreshing frequency


Holding time


Ratio of the maximum R OFF to R ON


Dopant mobility


Biasing voltage


Source to body voltage



The authors of this paper owe gratitude to ITM University Gwalior in Collaboration with Cadence Design System Bangalore for the support provided.


  1. 1.
    Tawfik, S., Liu, Z., & Kursun, V. (2007). Independent-gate and tied-gate FinFET SRAM circuits: Design guidelines for reduced area and enhanced stability. In 2007 International conference on microelectronics.Google Scholar
  2. 2.
    Helms, D., Schmidt, E., & Nebel, W. (2004). Leakage in CMOS circuits—An introduction. In E. Macii, V. Paliouras & O. Koufopavlou (Eds.), Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, (Vol. 3254). Berlin, Heidelberg: Springer.Google Scholar
  3. 3.
    Haraszti, T. (2000). CMOS memory circuits. Boston: Kluwer Academic.Google Scholar
  4. 4.
    Sakode, V., Lombardi, F., & Han, J. (2012). Cell design and comparative evaluation of a novel 1T memristor-based memory. In Proceedings of the 2012 IEEE/ACM international symposium on nanoscale architecturesNANOARCH ‘12.Google Scholar
  5. 5.
    Rabaey, J., & Pedram, M. (1996). Low power design methodologies. Boston: Kluwer Academic Publishers.CrossRefGoogle Scholar
  6. 6.
    Akashe, S., & Sharma, S. (2012). Leakage current reduction techniques for 7T SRAM cell in 45 nm technology. Wireless Personal Communications, 71(1), 123–136.CrossRefGoogle Scholar
  7. 7.
    Kao, J., & Chandrakasan, A. (2000). Dual-threshold voltage techniques for low-power digital circuits. IEEE Journal of Solid-State Circuits, 35(7), 1009–1018.CrossRefGoogle Scholar
  8. 8.
    Yeap, G. (1998). Practical low power digital VLSI design. Boston, MA: Kluwer Academic Publishers.CrossRefGoogle Scholar
  9. 9.
    Roy, K., & Prasad, S. (2000). Low-power CMOS VLSI circuit design. New York: Wiley.Google Scholar
  10. 10.
    Atsumi, S., Umezawa, A., Tanzawa, T., Taura, T., Shiga, H., Takano, Y., et al. (2000). A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme. IEEE Journal of Solid-State Circuits, 35(11), 1648–1654.CrossRefGoogle Scholar
  11. 11.
    Sakurai, T., & Newton, A. (1990). Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE Journal of Solid-State Circuits, 25(2), 584–594.CrossRefGoogle Scholar
  12. 12.
    Liu, D., & Svensson, C. (1993). Trading speed for low power by choice of supply and threshold voltages. IEEE Journal of Solid-State Circuits, 28(1), 10–17.CrossRefGoogle Scholar
  13. 13.
    Lee, D., Jun, Y., & Kong, B. (2011). Simultaneous reverse body and negative word-line biasing control scheme for leakage reduction of DRAM. IEEE Journal of Solid-State Circuits, 46(10), 2396–2405.CrossRefGoogle Scholar
  14. 14.
    Baker, R., Li, H., & Boyce, D. (1998). CMOS circuit design, layout, and simulation. New York: IEEE Press.Google Scholar
  15. 15.
    Streetman, B. (1980). Solid state electronic devices. Englewood Cliffs, NJ: Prentice-Hall.Google Scholar
  16. 16.
    Tsividis, Y. (1987). Operation and modeling of the MOS transistor. New York: McGraw-Hill.Google Scholar
  17. 17.
    Priya, M., Baskaran, K., & Krishnaveni, D. (2012). Leakage power reduction techniques in deep submicron technologies for VLSI applications. Procedia Engineering, 30, 1163–1170.CrossRefGoogle Scholar
  18. 18.
    Paliouras, V., Vounckx, J., & Verkest, D. (2005). Integrated circuit and system design. Berlin: Springer.Google Scholar
  19. 19.
    Abdollahi, A., Fallah, F., & Pedram, M. (2004). Leakage current reduction in CMOS VLSI circuits by input vector control. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(2), 140–154.CrossRefGoogle Scholar
  20. 20.
    Johnson, M., Somasekhar, D., Chiou, L.-Y., & Roy, K. (2002). Leakage control with efficient use of transistor stacks in single threshold CMOS. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(1), 1–5.CrossRefGoogle Scholar
  21. 21.
    Weste, N., Harris, D., & Weste, N. (2005). CMOS VLSI design. Boston: Pearson/Addison-Wesley.Google Scholar
  22. 22.
    Chua, L. (1971). Memristor-the missing circuit element. IEEE Transactions on Circuit Theory, 18(5), 507–519.CrossRefGoogle Scholar
  23. 23.
    Chua, L., & Kang, S. M. (1976). Memristive devices and systems. Proceedings of the IEEE, 64(2), 209–223.MathSciNetCrossRefGoogle Scholar
  24. 24.
    Sarwar, S., Saqueb, S., Quaiyum, F., & Rashid, A. (2013). Memristor-based nonvolatile random access memory: Hybrid architecture for low power compact memory design. IEEE Access, 1, 29–34.CrossRefGoogle Scholar
  25. 25.
    Hamdioui, S., Taouil, M., & Haron, N. (2015). Testing open defects in memristor-based memories. IEEE Transactions on Computers, 64(1), 247–259.MathSciNetCrossRefGoogle Scholar
  26. 26.
    Zhao, W., Portal, J., Kang, W., Moreau, M., Zhang, Y., Aziza, H., et al. (2014). Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells. Journal of Parallel and Distributed Computing, 74(6), 2484–2496.CrossRefGoogle Scholar
  27. 27.
    Cho, K., Lee, S., & Eshraghian, K. (2015). Memristor-CMOS logic and digital computational components. Microelectronics Journal, 46(3), 214–220.CrossRefGoogle Scholar
  28. 28.
    Chua, L. (2012). The fourth element. Proceedings of the IEEE, 100(6), 1920–1927.CrossRefGoogle Scholar
  29. 29.
    Prodromakis, T., Toumazou, C., & Chua, L. (2012). Two centuries of memristors. Nature Materials, 11(6), 478–481.CrossRefGoogle Scholar
  30. 30.
    Borghetti, J., Snider, G., Kuekes, P., Yang, J., Stewart, D., & Williams, R. (2010). ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature, 464(7290), 873–876.CrossRefGoogle Scholar
  31. 31.
    Biolek, D., Biolek, Z., Biolkova, V., & Kolka, Z. (2013). Some fingerprints of ideal memristors. In 2013 IEEE international symposium on circuits and systems (ISCAS2013).Google Scholar
  32. 32.
    Abdoli, B., Amirsoleimani, A., Shamsi, J., Mohammadi, K., & Ahmadi, A. (2014). A novel CMOS-memristor based inverter circuit design. In 2014 22nd Iranian conference on electrical engineering (ICEE).Google Scholar
  33. 33.
    Kvatinsky, S., Satat, G., Wald, N., Friedman, E., Kolodny, A., & Weiser, U. (2014). Memristor-based material implication (IMPLY) logic: Design principles and methodologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(10), 2054–2066.CrossRefGoogle Scholar
  34. 34.
    Williams, R. (2008). How we found the missing memristor. IEEE Spectrum, 45(12), 28–35.CrossRefGoogle Scholar
  35. 35.
    Radwan, A., & Fouda, M. (2015). On the mathematical modeling of memristor, memcapacitor, and meminductor. Studies in Systems, Decision and Control (Vol. 26, pp. 1–231). Springer.Google Scholar
  36. 36.
    Strukov, D., Snider, G., Stewart, D., & Williams, R. (2008). The missing memristor found. Nature, 453(7191), 80–83.CrossRefGoogle Scholar
  37. 37.
    Adhikari, S., Sah, M., Kim, H., & Chua, L. (2013). Three fingerprints of memristor. IEEE Transactions on Circuits and Systems I, 60(11), 3008–3021.CrossRefGoogle Scholar
  38. 38.
    Mutlu, R., & Karakulak, E. (2014). A methodology for memristance calculation. Turkish Journal of Electrical Engineering & Computer Sciences, 22, 121–131.CrossRefGoogle Scholar
  39. 39.
    Halawani, Y., Mohammad, B., Homouz, D., Al-Qutayri, M., & Saleh, H. (2016). Modeling and optimization of memristor and STT-RAM-based memory for low-power applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(3), 1003–1014.CrossRefGoogle Scholar
  40. 40.
    Cavin, R., Lugli, P., & Zhirnov, V. (2012). Science and engineering beyond moore’s law. In Proceedings of the IEEE (Vol. 100, pp. 1720–1749).Google Scholar
  41. 41.
    Linn, E., Rosezin, R., Tappertzhofen, S., Bottger, U., & Waser, R. (2012). Beyond von Neumann-logic operations in passive crossbar arrays alongside memory operations. Nanotechnology, 23(30), 305205.CrossRefGoogle Scholar
  42. 42.
    Ho, Y., Huang, G., & Li, P. (2011). Dynamical properties and design analysis for nonvolatile memristor memories. IEEE Transactions on Circuits and Systems I, 58(4), 724–736.MathSciNetCrossRefGoogle Scholar
  43. 43.
    Ibrayev, T., Fedorova, I., Maan, A., & James, A. (2014). On design of memristive amplifier circuits. Circuits and Systems, 5(11), 265–273.CrossRefGoogle Scholar
  44. 44.
    Eshraghian, K., Cho, K., Kavehei, O., Kang, S., Abbott, D., & Kang, S. (2011). Memristor MOS content addressable memory (MCAM): Hybrid architecture for future high performance search engines. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(8), 1407–1417.CrossRefGoogle Scholar
  45. 45.
    Ho, Y., Huang, G., & Li, P. (2009). Nonvolatile memristor memory. In Proceedings of the 2009 international conference on computer-aided designICCAD ‘09.Google Scholar
  46. 46.
    Wei, W., Namba, K., & Lombardi, F. (2013). Extending non-volatile operation to DRAM cells. IEEE Access, 1, 758–769.CrossRefGoogle Scholar
  47. 47.
    Mohammad, B., Homouz, D., Rayahi, O., Elgabra, H., & Hosani, A. (2011). Hybrid memristor-CMOS memory cell: Modeling and design. In ICM 2011 Proceeding.Google Scholar
  48. 48.
    Homouz, D., Mohammad, B., Elgabra, H., & Farahat, I. (2011). Memristor: Modeling read and write operations. In ICM 2011 Proceeding.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2017

Authors and Affiliations

  1. 1.Department of Electronic EngineeringHarare Institute of TechnologyHarareZimbabwe
  2. 2.Department of Electronics and Communication EngineeringITM UniversityGwaliorIndia

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