Skip to main content

CTHS Based Energy Efficient Thermal Aware Image ALU Design on FPGA

Abstract

Image ALU is a special type of ALU exclusively designed to perform arithmetic and logical operation on Image only. This Image ALU design is able to perform 14 operations. In this work, we have proposed a novel 4-stages energy efficient CTHS (C-Capacitance Scaling, T-Thermal Scaling, H-HSTL I/O Standard, S-SSTL I/O Standard) approach for Low Power and Thermal Aware Image ALU Design. CTHS technique is achieving 81.79 % reduction in power consumption which is more than the power reduction by method discussed in Shrivastava et al. (IEEE Trans Very Large Scale Integr Syst 18(6):988–997, 2010); Yoonjin and Mahapatra (IEEE Trans Very Large Scale Integr Syst 18(1):15–28, 2010); Chatterjee and Sachdev (IEEE Trans Very Large Scale Integr Syst 13(11):1296–1304, 2005); Wijeratne et al. (IEEE J Solid State Circuits 42(1):26–37, 2007); Nehru et al. (International conference on advances in engineering, science and management pp 145–149, 2012); Ho et al. (IEEE international symposium on circuits and systems pp 353–356, 2013); Rani et al. (3rd in international conference on electronics computer technology pp 224–228, 2011) for ALU. There is 38.63 % reduction in I/O Power and 46.42 % reduction in leakage power, when we scale down capacitance from 50 to 5 pF on 28 nm technology based Kintex-7 FPGA on 100 GHz device operating frequency. FPGA is a Filed Programmable Gate Array. There is 67.05 % reduction in I/O Power when we scale down ambient temperature from 50 to 10 °C on 100 GHz frequency. There are 5 different climates in koppen climate classification. We are taking 5 different values in order to nearly represent 5 climates. Using high profile Heat Sink and 500 LFM Airflow, there is 75.39 % leakage power reduction from the last optimized result of capacitance scaling and 85.84 % leakage power reduction from the initial power dissipation. On 3rd stage, using HSTL I/O Standard, there is 64.53 % power reduction from the initial power dissipation. There is 41.06, 59.26, 78.75 % power reduction from HSTL_II_DCI_18 to HSTL_I_12 on 100, 10 and 1 GHz. On 4th and final stage, using SSTL I/O Standard, there is 81.79 % power reduction from the initial power dissipation. There is 61.83 % reduction in junction temperature, when we apply 500 LFM airflow and high profile heat sink in compare to 250 LFM airflow and no heat sink. LFM is an acronym for Linear Feet per Minute. LFM is a unit of airflow that help us to control junction temperature of FPGA. Unit of leakage power is Watt (W) and Junction Temperature is degree Celsius (°C).

This is a preview of subscription content, access via your institution.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21
Fig. 22
Fig. 23
Fig. 24
Fig. 25
Fig. 26
Fig. 27
Fig. 28
Fig. 29
Fig. 30
Fig. 31
Fig. 32
Fig. 33

References

  1. 1.

    Shrivastava, A., Kannan, D., Bhardwaj, S., & Vrudhula, S. (2010). Reducing functional unit power consumption and its variation using leakage sensors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(6), 988–997.

    Article  Google Scholar 

  2. 2.

    Yoonjin, K., & Mahapatra, R. N. (2010). Dynamic context compression for low-power coarse-grained reconfigurable architecture. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(1), 15–28.

    Article  Google Scholar 

  3. 3.

    Chatterjee, B., & Sachdev, M. (2005). Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(11), 1296–1304.

    Article  Google Scholar 

  4. 4.

    Wijeratne, S. B., et al. (2007). A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit. IEEE Journal of Solid-State Circuits, 42(1), 26–37.

    Article  Google Scholar 

  5. 5.

    Nehru, K., Shanmugam, A., & Thenmozhi, G.D. (2012). Design of low power ALU using 8T FA and PTL based MUX circuits. In international conference on advances in engineering, science and management (ICAESM) (pp. 145–149).

  6. 6.

    Ho, W., Chong, K., Gwee, B., & Chang, J.S. (2013). Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU. In IEEE international symposium on circuits and systems (ISCAS), (pp. 353–356).

  7. 7.

    Rani, T.E., Rani, M.A., & Rao, R. (2011). AREA optimized low power arithmetic and logic unit. In 3rd international conference on electronics computer technology (ICECT) (pp. 224–228).

  8. 8.

    Kulkarni, M., Sheth, K., & Agrawal, V.D., (2011). Architectural power management for high leakage technologies. In IEEE 43rd southeastern symposium on system theory (SSST) (pp. 67–72).

  9. 9.

    Zhang, B., Mei, K., & Zheng, N. (2013). Reconfigurable processor for binary image processing. IEEE Transactions on Circuits and Systems for Video Technology, 23(5), 823–831.

    Article  Google Scholar 

  10. 10.

    Shan, D., Ibrahim, M., Shehata, M., & Badawy, W. (2013). Automatic license plate recognition (ALPR): A state-of-the-art review. IEEE Transactions on Circuits and Systems for Video Technology, 23(5), 311–325.

    Google Scholar 

  11. 11.

    Sullivan, G. J., Ohm, J., Han, W. J., & Wiegand, T. (2012). Overview of the high efficiency video coding (HEVC) standard. IEEE Transactions on Circuits and Systems for Video Technology, 22(12), 1649.

    Article  Google Scholar 

  12. 12.

    Chen, S. L. (2013). VLSI implementation of an adaptive edge-enhanced image scalar for real-time multimedia applications. IEEE Transactions on Circuits and Systems for Video Technology, 23(9), 1510–1522.

    Article  Google Scholar 

  13. 13.

    Bossen, F., Bross, B., Suhring, K., & Flynn, D. (2012). HEVC complexity and implementation analysis. IEEE Transactions on Circuits and Systems for Video Technology, 22(12), 1685–1696.

    Article  Google Scholar 

  14. 14.

    Pushe, Z., Hongbo, Z., He, L., & Shibata, T. (2013). A directional-edge-based real-time object tracking system employing multiple candidate-location generation. IEEE Transactions on Circuits and Systems for Video Technology, 23(3), 503–517.

    Article  Google Scholar 

  15. 15.

    Wang, L., et al. (2013). Edge-directed single-image super-resolution via adaptive gradient magnitude self-interpolation. IEEE Transactions on Circuits and Systems for Video Technology, 23(8), 1289–1299.

    Article  Google Scholar 

  16. 16.

    Lainema, J., Bossen, F., Woo-Jin, H., Junghye, M., & Ugur, K. (2012). Intra coding of the HEVC standard. IEEE Transactions on Circuits and Systems for Video Technology, 22(12), 1792–1801.

    Article  Google Scholar 

  17. 17.

    Tian, J. (2013). Reversible data embedding using a difference expansion. IEEE Transactions on Circuits and Systems for Video Technology, 13(8), 890–896.

    Article  Google Scholar 

  18. 18.

    Choi, M., Chang, I. J., & Kim, J. (2013). High performance and hardware efficient multiview video coding frame scheduling algorithms and architectures. IEEE Transactions on Circuits and Systems for Video Technology, 23(8), 1312–1321.

    Article  Google Scholar 

  19. 19.

    Sjoberg, R., et al. (2012). Overview of HEVC high-level syntax and reference picture management. IEEE Transactions on Circuits and Systems for Video Technology, 22(12), 1858–1870.

    Article  Google Scholar 

  20. 20.

    Peng, W. H., & Chen, C. C. (2013). An interframe prediction technique combining template matching prediction and block-motion compensation for high-efficiency video coding. IEEE Transactions on Circuits and Systems for Video Technology, 23(8), 1432–1446.

    Article  Google Scholar 

  21. 21.

    Jung, S. W. (2013). Enhancement of image and depth map using adaptive joint trilateral filter. IEEE Transactions on Circuits and Systems for Video Technology, 23(2), 258–269.

    Article  Google Scholar 

  22. 22.

    Zhou, M., et al. (2012). HEVC lossless coding and improvements. IEEE Transactions on Circuits and Systems for Video Technology, 22(12), 1839–1843.

    Article  Google Scholar 

  23. 23.

    Chuan, Q. (2013). An inpainting-assisted reversible steganographic scheme using a histogram shifting mechanism. IEEE Transactions on Circuits and Systems for Video Technology, 23(7), 1109–1118.

    Article  Google Scholar 

  24. 24.

    Series FPGA SelectIO Resources User Guide UG361 (v1.4) June 21, 2013http://japan.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

  25. 25.

    Gupta, V., Mohapatra, D., Raghunathan, A., & Roy, K. (2013). Low-power digital signal processing using approximate adders. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(1), 124–137.

    Article  Google Scholar 

  26. 26.

    Suming, L., Yan, B., & Li, P. (2013). Localized stability checking and design of IC power delivery with distributed voltage regulators. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(9), 1321–1324.

    Article  Google Scholar 

  27. 27.

    Singh, D., Pattanaik, M., & Pandey, B., (2013). IO standard based low power design of RAM and implementation on FPGA. Journal of Automation and Control Engineering, 1(4), 316–320.

  28. 28.

    Esmaeili, S. E., & Al Kahlili, A. J. (2013). Integrated power and clock distribution network. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(10), 1941–1945.

    Article  Google Scholar 

  29. 29.

    Pandey, B., Yadav, J., Singh, Y., Kumar, R., & Patel, S. (2013). Energy Efficient Design and Implementation of ALU on 40-nm FPGA. IEEE international conference on energy efficient technologies for sustainability-(ICEETs).

  30. 30.

    Singh, V.P., Chaurasia, V. S., Pandey, B., & Yadav, J. (2013). Power reduction of ITC’99-b01 benchmark circuit using clock gating techniques. In IEEE international conference on computational intelligence and communication networks (CICN), Mathura.

  31. 31.

    Kumar, T., et al. (2014). Mobile DDR IO standard based high performance energy efficient portable alu design on FPGA. Springer Wireless Personal Communications, An International Journal, 76(3), 569–578.

    Article  Google Scholar 

Download references

Author information

Affiliations

Authors

Corresponding author

Correspondence to Tanesh Kumar.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Kumar, T., Pandey, B., Mussavi, S.H.A. et al. CTHS Based Energy Efficient Thermal Aware Image ALU Design on FPGA. Wireless Pers Commun 85, 671–696 (2015). https://doi.org/10.1007/s11277-015-2801-8

Download citation

Keywords

  • Low power design
  • Energy efficiency
  • Capacitance scaling
  • Thermal analysis
  • HSTL
  • SSTL IO Standard
  • Real time image processing
  • FPGA