Wireless Personal Communications

, Volume 85, Issue 3, pp 671–696 | Cite as

CTHS Based Energy Efficient Thermal Aware Image ALU Design on FPGA

  • Tanesh Kumar
  • Bishwajeet Pandey
  • S. H. A. Mussavi
  • Noor Zaman
Article

Abstract

Image ALU is a special type of ALU exclusively designed to perform arithmetic and logical operation on Image only. This Image ALU design is able to perform 14 operations. In this work, we have proposed a novel 4-stages energy efficient CTHS (C-Capacitance Scaling, T-Thermal Scaling, H-HSTL I/O Standard, S-SSTL I/O Standard) approach for Low Power and Thermal Aware Image ALU Design. CTHS technique is achieving 81.79 % reduction in power consumption which is more than the power reduction by method discussed in Shrivastava et al. (IEEE Trans Very Large Scale Integr Syst 18(6):988–997, 2010); Yoonjin and Mahapatra (IEEE Trans Very Large Scale Integr Syst 18(1):15–28, 2010); Chatterjee and Sachdev (IEEE Trans Very Large Scale Integr Syst 13(11):1296–1304, 2005); Wijeratne et al. (IEEE J Solid State Circuits 42(1):26–37, 2007); Nehru et al. (International conference on advances in engineering, science and management pp 145–149, 2012); Ho et al. (IEEE international symposium on circuits and systems pp 353–356, 2013); Rani et al. (3rd in international conference on electronics computer technology pp 224–228, 2011) for ALU. There is 38.63 % reduction in I/O Power and 46.42 % reduction in leakage power, when we scale down capacitance from 50 to 5 pF on 28 nm technology based Kintex-7 FPGA on 100 GHz device operating frequency. FPGA is a Filed Programmable Gate Array. There is 67.05 % reduction in I/O Power when we scale down ambient temperature from 50 to 10 °C on 100 GHz frequency. There are 5 different climates in koppen climate classification. We are taking 5 different values in order to nearly represent 5 climates. Using high profile Heat Sink and 500 LFM Airflow, there is 75.39 % leakage power reduction from the last optimized result of capacitance scaling and 85.84 % leakage power reduction from the initial power dissipation. On 3rd stage, using HSTL I/O Standard, there is 64.53 % power reduction from the initial power dissipation. There is 41.06, 59.26, 78.75 % power reduction from HSTL_II_DCI_18 to HSTL_I_12 on 100, 10 and 1 GHz. On 4th and final stage, using SSTL I/O Standard, there is 81.79 % power reduction from the initial power dissipation. There is 61.83 % reduction in junction temperature, when we apply 500 LFM airflow and high profile heat sink in compare to 250 LFM airflow and no heat sink. LFM is an acronym for Linear Feet per Minute. LFM is a unit of airflow that help us to control junction temperature of FPGA. Unit of leakage power is Watt (W) and Junction Temperature is degree Celsius (°C).

Keywords

Low power design Energy efficiency Capacitance scaling Thermal analysis HSTL SSTL IO Standard Real time image processing FPGA 

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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Tanesh Kumar
    • 1
  • Bishwajeet Pandey
    • 2
  • S. H. A. Mussavi
    • 1
  • Noor Zaman
    • 3
  1. 1.Indus UniversityKarachiPakistan
  2. 2.School of Electrical and Electronics EngineeringChitkara UniversityChandigarhIndia
  3. 3.CCSITKing Faisal UniversityAl-HasaSaudi Arabia

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