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DCBuf: a high-performance wireless network-on-chip architecture with distributed wireless interconnects and centralized buffer sharing

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Abstract

Wireless Network-on-Chips (WiNoCs) were expected to handle the communication requirements of the long-distance processing elements. Hence, high-performance WiNoC designs that achieve low-latency and high-throughput are crucial for future performance requirements. The size and organization of the buffer directly affects network performance, while the buffer also determines the area overhead of the router. We propose DCBuf, a distributed CNT-based (Carbon nanotubes) inter-subnet wireless interconnects and centralized intra-port buffer sharing architecture for a symmetry Wireless Network-on-Chip. The centrosymmetric wireless hub structure combined with CNT-based wireless interconnects maximizes the performance ceiling of WiNoC. Moreover, this approach allows to reuse the table-based shared-buffer for different traffic while ensuring that minimizes buffering requirements without sacrificing performance. The architecture uses just two registers per private VC and a shared buffer sized large enough to cover the demand of different traffic that appears either on the NoC links or due to the internal pipeline of the NoC buffers. In this perspective, the shared buffer within an input-port is considered space queues not statically assigned to a specific VC. Cycle-accurate network simulations including both synthetic traffic patterns and real application workloads running in a full-system simulation framework validate the efficacy and efficiency of the proposed architecture.

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Data availability statement

Some or all data, models, or code generated or used during the study are available from the corresponding author by request.

References

  1. Borkar, S. (2007). Thousand core chips: a technology perspective. Proceedings of the 44th annual design automation conference, pp 746–749

  2. Dally, W. J., & Towles, B. P. (2004). Principles and practices of interconnection networks. Elsevier.

  3. Ogras, U. Y. (2013). Dissertation: Modeling, analysis and optimization of network-on-chip. dissertations & theses gradworks.

  4. Deb, S., Ganguly, A., Pande, P. P., et al. (2012). Wireless NoC as interconnection backbone for multicore chips: Promises and challenges. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2(2), 228–239.

    Article  Google Scholar 

  5. Ganguly, A., Chang, K., Deb, S., et al. (2010). Scalable hybrid wireless network-on-chip architectures for multicore systems. IEEE Transactions on Computers, 60(10), 1485–1502.

    Article  MathSciNet  Google Scholar 

  6. Lee, B. G., Chen, X., Biberman, A., et al. (2008). Ultrahigh-bandwidth silicon photonic nanowire waveguides for on-chip networks. IEEE Photonics Technology Letters, 20(6), 398–400.

    Article  Google Scholar 

  7. Wu, Y., Liu, L., Wang, L., et al. (2020). Aggressive Fine-Grained Power Gating of NoC Buffers. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(11), 3177–3189.

    Article  Google Scholar 

  8. Nicopoulos, C. A., Park, D., Kim, J., ViChaR: A dynamic virtual channel regulator for network-on-chip routers., et al. (2006). 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’06). IEEE, 2006, 333–346.

    Google Scholar 

  9. Chen, X., Peh, L.S. (2003). Leakage power modeling and optimization in interconnection networks [C]. Proceedings of the 2003 international symposium on Low power electronics and design, pp. 90–95.

  10. Zoni, D., Flich, J., & Fornaciari, W. (2015). Cutbuf: Buffer management and router design for traffic mixing in vnet-based nocs. IEEE Transactions on Parallel and Distributed Systems, 27(6), 1603–1616.

    Article  Google Scholar 

  11. Ye, T. T., Micheli, G. D., & Benini, L. (2002). Analysis of power consumption on switch fabrics in network routers. Proceedings of the 39th annual design automation conference, pp. 524–529.

  12. Grot, B., Hestness, J., Keckler, S. W., et al. (2009). Express cube topologies for on-chip interconnects. 2009 IEEE 15th international symposium on high performance computer architecture. IEEE, pp. 163–174.

  13. Kim, J., Park, D., Theocharides, T, et al. (2005). A low latency router supporting adaptivity for on-chip interconnects. Proceedings 42nd design automation conference, 2005. IEEE, pp. 559–564.

  14. Jain, A., Laxmi, V., Tripathi, M., et al. (2020). TRACK: An algorithm for fault-tolerant, dynamic and scalable 2D mesh network-on-chip routing reconfiguration. Integration, 72, 92–110.

    Article  Google Scholar 

  15. Peh, L. S., & Dally, W. J. (2001). A delay model and speculative architecture for pipelined routers. Proceedings HPCA seventh international symposium on high-performance computer architecture. IEEE, pp. 255–266.

  16. Galles, M. (1997). Spider: A high-speed network interconnect. IEEE Micro, 17(1), 34–39.

    Article  MathSciNet  Google Scholar 

  17. Shi, W., Xu, W., Ren, H., et al. (2011). A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer. 2011 IEEE 29th international conference on computer design (ICCD). IEEE, pp. 267–272.

  18. Huang, T. C., Ogras, U. Y., & Marculescu, R. (2007). Virtual channels planning for networks-on-chip. 8th International symposium on quality electronic design (ISQED'07). IEEE, pp. 879–884.

  19. Rezazad, M., & Sarbazi-Azad, H. (2005). The effect of virtual channel organization on the performance of interconnection networks. 19th IEEE international parallel and distributed processing symposium. IEEE, 8 pp.

  20. Concatto, C., Kologeski, A., Carro, L., et al. (2011). Two-levels of adaptive buffer for virtual channel router in nocs. 2011 IEEE/IFIP 19th international conference on VLSI and system-on-chip. IEEE, pp. 302–307.

  21. Seitanidis, I., Psarras, A., Chrysanthou, K., et al. (2015). ElastiStore: Flexible elastic buffering for virtual-channel-based networks on chip. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(12), 3015–3028.

  22. Jindal, N., Gupta, S., Ravipati, D. P., et al. (2019). Enhancing Network-on-Chip performance by reusing trace buffers. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(4), 922–935.

    Article  Google Scholar 

  23. Nguyen, S. T., & Oyanagi, S. (2010). A low cost single-cycle router based on virtual output queuing for on-chip networks. 2010 13th Euromicro conference on digital system design: Architectures, methods and tools. IEEE, pp. 60–67.

  24. Zhao, D., & Wang, Y. (2008). SD-MAC: Design and synthesis of a hardware-efficient collision-free QoS-aware MAC protocol for wireless network-on-chip. IEEE Transactions on Computers, 57(9), 1230–1245.

    Article  MathSciNet  Google Scholar 

  25. Chang, K., Deb, S., Ganguly, A., et al. (2012). Performance evaluation and design trade-offs for wireless network-on-chip architectures. ACM Journal on Emerging Technologies in Computing Systems (JETC), 8(3), 1–25.

    Article  Google Scholar 

  26. Lee, S. B., Tam, S. W., Pefkianakis, I., et al. (2009). A scalable micro wireless interconnect structure for CMPs. Proceedings of the 15th annual international conference on Mobile computing and networking, pp. 217–228.

  27. DiTomaso, D., Kodi, A., Kaya, S., et al. (2011). iWISE: Inter-router wireless scalable express channels for network-on-chips (NoCs) architecture. 2011 IEEE 19th annual symposium on high performance interconnects. IEEE, pp. 11–18.

  28. Mondal, H. K., et al. (2017). Adaptive multi-voltage scaling with utilization prediction for energy-efficient wireless noc. IEEE Transactions on Sustainable Computing, 2(4), 382–395.

    Article  Google Scholar 

  29. Abadal, S., et al. (2017). OrthoNoC: A broadcast-oriented dual-plane wireless network-on-chip architecture. IEEE Transactions on Parallel and Distributed Systems, 29(3), 628–641.

    Article  Google Scholar 

  30. DiTomaso, D., et al. (2014). A-winoc: Adaptive wireless network-on-chip architecture for chip multiprocessors. IEEE Transactions on Parallel and Distributed Systems, 26(12), 3289–3302.

    Article  Google Scholar 

  31. Catania, V., et al. (2016). Cycle-accurate network on chip simulation with noxim. ACM Transactions on Modeling and Computer Simulation (TOMACS), 27(1), 1–25.

    Article  MathSciNet  Google Scholar 

  32. Deb, S., et al. (2012). Design of an energy-efficient CMOS-compatible NoC architecture with millimeter-wave wireless interconnects. IEEE Transactions on Computers, 62(12), 2382–2396.

    Article  MathSciNet  Google Scholar 

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Funding

This study was funded by the National Natural Science Foundation of China (NSFC) research Projects (Grant Number 61874157).

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Authors and Affiliations

  1. School of Computer and Information, Hefei University of Technology, Hefei, 230009, China

    Chenglong Sun & Yiming Ouyang

  2. School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei, 230009, China

    Yingchun Lu

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  1. Chenglong Sun
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Correspondence to Chenglong Sun.

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Sun, C., Ouyang, Y. & Lu, Y. DCBuf: a high-performance wireless network-on-chip architecture with distributed wireless interconnects and centralized buffer sharing. Wireless Netw 28, 505–520 (2022). https://doi.org/10.1007/s11276-021-02882-x

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