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Low area FPGA implementation of PRESENT cryptography with 3S-RLKG and MKS

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Abstract

Nowadays, security and confidentiality are considered as important aspects throughout the growth of computerized systems, information technology, and internet communication. The cryptographic algorithms are used to improve the security against various threats/attacks (e.g., differential attacks and statistical attacks). In this research, the modified PRESENT architecture is proposed to improve the security against unauthorized users while minimizing the hardware utilization. The PRESENT architecture is modified by proposing three key strategies; (1) three Stage Reversible Logic Key Generation (3S-RLKG) is developed to generate the optimal key value using three different gates such as Feynman gate, DFG gate and Toffoli gate, (2) Modified Key Scheduling (MKS) and Bit Reversible Function (BRF) is additionally used in the PRESENT architecture to increase the confusion property and (3) mitigation of the Read-Only Memory (ROM) to store the intermediate values in the Field Programmable Gate Array (FPGA) processor. Therefore, the higher confusion property leads to an increase in the security against the unauthorized users. The performance of 3S-RLKG-PRESENT architecture is evaluated by means of the number of slice registers, flip flops, number of Look Up Table (LUT), number of logical elements, slices and bonded input/output block (IOB). Moreover, the 3S-RLKG-PRESENT architecture is also analyzed in the Spartan 6 XC6SLX9 -2 TQG144 FPGA hardware. The 3S-RLKG-PRESENT architecture is compared with different existing PRESENT architectures namely Maximum Distance Separable (MDS) based PRESENT, PRESENT, PRESENT with X Compactor, PRESENT- Round Key Generation (RKG), PRESENT- Storage Mode (SM) and Pseudo Random Bit Generator (PRBG). The 3S-RLKG-PRESENT designed in the Spartan 6 consumes 131 LUTs, 70 flip flops and 48 slices which are less when compared to the PRESENT-RKG.

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  1. Department of Electronics and Telematics Engineering, G. Narayanamma Institute of Technology and Science, Shaikpet, Hyderabad, India

    Sunitha Tappari

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  1. Sunitha Tappari
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Tappari, S. Low area FPGA implementation of PRESENT cryptography with 3S-RLKG and MKS. Wireless Netw 27, 5397–5416 (2021). https://doi.org/10.1007/s11276-021-02797-7

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