A fault-tolerant and congestion-aware architecture for wireless networks-on-chip

Abstract

The combination of traditional wired links for regular transmissions and express wireless paths for long distance communications is a promising solution to prevent multi-hop network delays. In wireless network-on-chip technology, wireless-equipped routers are more error-prone than the conventional ones not only because of their implementation complexities but also due to their relatively high utilization. In this paper, a new topology is presented to enhance the network reliability, and then a novel routing algorithm is proposed to tolerate both intermittent and permanent faults on wireless hubs. In the proposed approach, once a wireless hub becomes faulty, the best alternative adjustment hub will be indicated and all the packets that have high average hop-count are routed through this alternative hub. In comparison with the state-of-the-art works, the proposed approach shows significant improvements in terms of robustness, congestion management, and resilience.

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Correspondence to Farshad Safaei.

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Mortazavi, S.H., Akbar, R., Safaei, F. et al. A fault-tolerant and congestion-aware architecture for wireless networks-on-chip. Wireless Netw 25, 3675–3687 (2019). https://doi.org/10.1007/s11276-019-01962-3

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Keywords

  • Network-on-chip
  • Hybrid wireless network-on-chip
  • Many-core system-on-chip
  • Reliability
  • Robustness
  • Congestion control management