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A FAST Hardware Decoder Optimized for Template Features to Obtain Order Book Data in Low Latency

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Abstract

High-Frequency Trading (HFT) systems require high computational performance for real-time trading and data analysis. FAST protocol, an extension of FIX protocol, is one of the main communication pattern adopted by these systems. This work presents an open source hardware component, implemented in Field-Programmable Gate Array (FPGA), to decode market data messages to produce the necessary commands to construct order books in low latency for the Brasil Bolsa Balcão B3 stock exchange. The proposed hardware component optimized for a B3 template is able to decode messages at average latency of 0.72us and throughput of 1.4M FAST messages per second. The results are from logs of real messages with average size of 85 bytes each.

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Acknowledgements

The authors would like to thank CAPES for the financial support given to this research project.

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Authors and Affiliations

  1. Institute of Mathematical and Computing Sciences, The University of São Paulo, São Paulo, Brazil

    Caio C. S. Oliveira & Vanderlei Bonato

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  1. Caio C. S. Oliveira
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  2. Vanderlei Bonato
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Correspondence to Caio C. S. Oliveira.

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Oliveira, C.C.S., Bonato, V. A FAST Hardware Decoder Optimized for Template Features to Obtain Order Book Data in Low Latency. J Sign Process Syst 95, 559–567 (2023). https://doi.org/10.1007/s11265-023-01850-2

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  • DOI: https://doi.org/10.1007/s11265-023-01850-2

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