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A Fractional Sample Rate Converter with Parallelized Multiphase Output: Algorithm and FPGA Implementation

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Abstract

Sample rate conversion is an essential scheme used in almost every radio design. Supporting sampling rates higher than the clock rates require parallel processing. In this paper, we propose an algorithm for a sample rate converter (SRC) with multiple parallel output phases so that the conversion ratio can be a fixed rational number. Due to the structure of the proposed algorithm, it is suitable for embedded platforms which are restricted by their clock frequency but require very high sample rates. A dual phase output variant of the proposed algorithm is simulated with a 400 MHz input signal to perform a 15/8 conversion. The test and verification of the SRC algorithm is presented with the aid of a design example. A VLSI architecture of the dual phase output SRC is implemented on a Virtex-7 field-programmable gate array (FPGA) and results are presented.

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Notes

  1. Ideal interpolation can be done by FFT for a cyclic signal.

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Authors and Affiliations

  1. Mobile Networks, Nokia, Kaapelitie 4, Oulu, 90620, Finland

    Shahriar Shahabuddin

  2. Digital Enhancement Suomi Oy, Kiviharjunlenkki 1 B, Oulu, 90220, Finland

    Petri Manninen

  3. Centre for Wireless Communications, University of Oulu, Erkki Koiso-Kanttilan katu 3, Oulu, 90570, Finland

    Shahriar Shahabuddin & Markku Juntti

Authors
  1. Shahriar Shahabuddin
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  2. Petri Manninen
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  3. Markku Juntti
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Correspondence to Shahriar Shahabuddin.

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Shahabuddin, S., Manninen, P. & Juntti, M. A Fractional Sample Rate Converter with Parallelized Multiphase Output: Algorithm and FPGA Implementation. J Sign Process Syst 94, 1459–1469 (2022). https://doi.org/10.1007/s11265-022-01776-1

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  • DOI: https://doi.org/10.1007/s11265-022-01776-1

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