This paper proposes two decoder hardware architectures for the tabled asymmetric numeral systems (tANS) compression algorithm, a software implementation of which is used by Apple and Facebook due to its efficiency. To the best of our knowledge, hardware architectures for the highly efficient tANs algorithm are investigated by the authors so far uniquely. The tANS decoder hardware architectures have been compared to a novel Huffman decoder hardware architecture because the Huffman coding is known as one of the fastest coding techniques in hardware and software. For the proposed architectures, the decoding throughput is highly dependent on the compression ratio of data. Experimental results show that the proposed tANS architecture outperforms the tANS software decoder and can achieve the throughput up to 200MB/s using current FPGA technology. Compared to canonical Huffman decoder the proposed hardware architecture provides up to four times higher decoding throughput.
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The authors would like to thank the German Research Foundation (DFG) and the SimTech Cluster of the University of Stuttgart for the financial support of this project PN 2-6.
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Najmabadi, S.M., Tran, T., Eissa, S. et al. An Architecture for Asymmetric Numeral Systems Entropy Decoder - A Comparison with a Canonical Huffman Decoder. J Sign Process Syst 91, 805–817 (2019). https://doi.org/10.1007/s11265-018-1421-4
- Data compression
- Reconfigurable hardware architecture
- Asymmetric numeral systems
- Canonical huffman decoder