Abstract
Heterogeneous computing plays an ever-increasing role in power-efficient, high-performance embedded systems for various data processing tasks, such as computer vision. One possibility to accelerate this kind of application is the usage of FPGAs as a co-processor for standard CPUs. Although hardware design is becoming easier by utilizing High-Level-Synthesis tools, the question of interfacing FPGAs and CPUs has yet to be completely solved. The Heterogeneous System Architecture (HSA) Foundation defines and publishes architecture neutral standards for heterogeneous systems and programming models. While compatible CPU, GPU and DSP designs exist, FPGA models have not been defined yet. This paper describes the IP library LibHSA, which greatly simplifies integration of domain specific FPGA acceleration into existing HSA compliant systems. It allows FPGA based accelerators to take immediate advantage of high-level language tool chains. Including user space memory access, low-latency task dispatch and other benefits of the HSA programming model. We will demonstrate LibHSA with a programmable image processor implementation on a Xilinx FPGA. The image processor supports low-level algorithms, e.g. Sobel, Median, Laplace, or Gaussian. Our results show that the LibHSA infrastructure greatly simplifies the effort integrating FPGAs and customized hardware into existing accelerator systems, runtimes and application software.
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Reichenbach, M., Holzinger, P., Häublein, K. et al. Heterogeneous Computing Utilizing FPGAs. J Sign Process Syst 91, 745–757 (2019). https://doi.org/10.1007/s11265-018-1382-7
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DOI: https://doi.org/10.1007/s11265-018-1382-7