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A Faddeev Systolic Array for EKF-SLAM and its Arithmetic Data Representation Impact on FPGA

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Abstract

The Extended Kalman Filter (EKF) computation is a core task for the simultaneous localization and mapping (SLAM) problem in autonomous mobile robots. The SLAM problem involves operations over high dimension data sets, requiring high throughput and performance, given the real-time nature of the robotics, control-decision algorithm this task is a part of. The lightweight and power restricted computing environments in mobile robotics requires customized processing systems such as Field-Programmable Gate Arrays (FPGAs). This work presents an arithmetic precision analysis and a Faddeev algorithm to calculate the Schur’s Complement hardware architecture implementation for the EKF-SLAM using a Systolic Array (SA). While it is widely believed that fixed-point implementations of arithmetic operations lead to area and performance benefits on FPGAs, the results in this article reveal that each Processing Element (PE) in the SA consumes 25% more logic and about 30% more register resources for the fixed-point 13.23 representation than if using the IEEE-754 single precision floating-point format. In addition, for FPGA devices with hardware support for key components of floating-point computations, a single PE floating-point implementation can achieve a maximum frequency up to 50% higher than a corresponding fixed-point implementation for the same relative numeric errors.

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Notes

  1. We extend the representation of each fixed-point values from the n = m + p to be 2n so that the output of the multiplication has the same bit-width.

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Acknowledgments

The authors would like to thank FAPESP (Ref. 2012/20224-8) for the financial support given to develop this research project.

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Authors and Affiliations

  1. Institute of Mathematics and Computing Science, The University of São Paulo, São Paulo, Brazil

    Leandro de Souza Rosa, Aravind Dasu & Vanderlei Bonato

  2. Information Sciences Institute, University of Southern California, Los Angeles, CA, 90007, USA

    Aravind Dasu & Pedro C. Diniz

Authors
  1. Leandro de Souza Rosa
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  2. Aravind Dasu
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  3. Pedro C. Diniz
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  4. Vanderlei Bonato
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Corresponding author

Correspondence to Leandro de Souza Rosa.

Additional information

Dr. Aravid Dasu Currently is affiliated to Intel Corporation. Even though, the paper was written while he was part of the University of Southern California, which is them credited for.

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de Souza Rosa, L., Dasu, A., C. Diniz, P. et al. A Faddeev Systolic Array for EKF-SLAM and its Arithmetic Data Representation Impact on FPGA. J Sign Process Syst 90, 357–369 (2018). https://doi.org/10.1007/s11265-017-1243-9

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  • DOI: https://doi.org/10.1007/s11265-017-1243-9

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