Foreword to the Special Section on Reconfigurable Computing
In the past two decades, reconfigurable computing has evolved from a niche design technology to a mainstream computing technology, as testified by its use in datacenters and its availability in cloud computing infrastructures. The main reason is that thanks to its flexibility, reconfigurable hardware can serve many different application domains, from arithmetic-intensive digital signal-processing applications to narrow niche applications, such as enumerative combinatorics.
This special section of the Springer’s Journal of Signal Processing Systems (JSPS) illustrates the diversity in the field of reconfigurable computing with its five papers describing application-specific FPGA accelerators that span a wide spectrum of applications. The five papers presented in this special section are briefly summarized below.
The first paper, “A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s” by Maragos et al. (10.1007/s11265-016-1201-y), presents a high-performance FPGA-based architecture aimed at supporting optical interconnects in datacenters. Specifically, the work focuses on the problem of implementing the digital equalization stage, which is addressed through the use of a highly parallel implementation of a feed-forward equalizer (FFE). The results show that links up to 112 Gbps can be supported on state-of-the-art FPGA devices.
The second paper, “An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC” by Tsoutsouras et al. (10.1007/s11265-017-1230-1), describes a design exploration framework for Support Vector Machine FPGA accelerators. Their approach is based on High Level Synthesis technology, and is validated on a an ECG analysis and Arrhythmia detection system. Their exploration is performed at two levels, the first one at the behavioral level to expose data- and instruction-level parallelism, and the second one at the architectural level, given the target platform memory system characteristics. The resulting accelerator has been implemented on a Zynq programmable SoC and authors show that the FPGA implementation can achieve a speedup up to 78 × .
The next paper, “RImCom: Raster-order Image Compressor for Embedded Video Applications” by Ugurdag et al. (10.1007/s11265-016-1211-9), presents a hardware solution that enables real-time compression of raster-order video streams. The approach delivers compression factors of 66% in lossless and lossy modes, and is the the first approach to reach 60 fps at Full HD with rate control. Thanks to the proposed approach, on-the-fly compression/decompression can be used for processing HD video streams, thus lowering the pressure on the memory system and leading to reductions in system cost, electromagnetic radiation and power consumption.
In their paper “Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems”, El-Hadedy et al. (10.1007/s11265-016-1199-1) propose a novel register-based transpose memory architecture, in which the use of dual-edge clocked registers is one of the main contributions. This approach allows the circuit throughput to be doubled and improves the clock speed by eliminating the need for combinational logic. When applied in the context of 2D–DCT and 2D–IDCT blocks, the proposed approach brings a threefold speed-up while consuming 20% less area than previous work.
The fifth and the final paper, “Putting queens in carry chains, No. 27” by Thomas Preußer et al. (10.1007/s11265-016-1176-8), illustrates how FPGAs can also be used to help solve combinatorial problems. Their work, which is part of an open-source effort, aims at accelerating the search of solutions to a previously unsolved problem instance of the well-known N-Queens Puzzle. Their article describes how they partition the exploration space to enable efficient parallelization, and details how they could take advantage of the bit-level structure of FPGAs to solve this problem. An in-depth discussion of current results and a projection on the remaining run time to solve the problem are also provided in the paper.
Together, the five papers in this special section clearly demonstrates the relevance of reconfigurable computing for a wide range of application that arise in today’s computing landscape.
We would like to acknowledge the support of the Journal of Signal Processing Systems Editor in Chief, the contributions from the authors of the papers, and the help of the reviewers which was very appreciated and helped to improve the final quality of the papers.
We hope you enjoy reading the papers included in this special section.