Journal of Signal Processing Systems

, Volume 90, Issue 11, pp 1533–1549 | Cite as

Memory Controller for Vector Processor

  • Tassadaq HussainEmail author
  • Oscar Palomar
  • Osman S. Ünsal
  • Adrian Cristal
  • Eduard Ayguadé


To manage power and memory wall affects, the HPC industry supports FPGA reconfigurable accelerators and vector processing cores for data-intensive scientific applications. FPGA based vector accelerators are used to increase the performance of high-performance application kernels. Adding more vector lanes does not affect the performance, if the processor/memory performance gap dominates. In addition if on/off-chip communication time becomes more critical than computation time, causes performance degradation. The system generates multiple delays due to application’s irregular data arrangement and complex scheduling scheme. Therefore, just like generic scalar processors, all sets of vector machine – vector supercomputers to vector microprocessors – are required to have data management and access units that improve the on/off-chip bandwidth and hide main memory latency. In this work, we propose an Advanced Programmable Vector Memory Controller (PVMC), which boosts noncontiguous vector data accesses by integrating descriptors of memory patterns, a specialized on-chip memory, a memory manager in hardware, and multiple DRAM controllers. We implemented and validated the proposed system on an Altera DE4 FPGA board. The PVMC is also integrated with ARM Cortex-A9 processor on Xilinx Zynq All-Programmable System on Chip architecture. We compare the performance of a system with vector and scalar processors without PVMC. When compared with a baseline vector system, the results show that the PVMC system transfers data sets up to 1.40x to 2.12x faster, achieves between 2.01x to 4.53x of speedup for 10 applications and consumes 2.56 to 4.04 times less energy.


Vector processor Scalar core SDRAM controller 


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Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  • Tassadaq Hussain
    • 1
    • 2
    • 3
    • 4
    Email author
  • Oscar Palomar
    • 3
    • 4
  • Osman S. Ünsal
    • 3
  • Adrian Cristal
    • 3
    • 4
    • 5
  • Eduard Ayguadé
    • 3
    • 4
  1. 1.Riphah International UniversityIslamabadPakistan
  2. 2.Unal Color of Education Research and DevelopmentIslamabadPakistan
  3. 3.Computer Sciences, Barcelona Supercomputing CenterBarcelonaSpain
  4. 4.Departament d’Arquitectura de ComputadorsUniversitat Politècnica de CatalunyaBarcelonaSpain
  5. 5.Artificial Intelligence Research Institute (IIIA), Centro Superior de Investigaciones Científicas (CSIC)BarcelonaSpain

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