A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s

Abstract

Commodity optoelectronic components and multi-level modulation formats are combined nowadays in optical networks to increase their throughput while decreasing their cost. To overcome the inherent limitations of such interconnects, research focuses on digital equalizers that compensate for the effects of the developed channels. The current paper proposes the use of FPGAs to enhance the speed, power and flexibility of digital equalization for the next generation 100 Gb/s rack-to-rack optical links in datacenters. We present the high-performance hardware architecture of a flexible feed-forward equalizer (FFE) with multiple reconfigurations. We describe parallelization techniques to accelerate FFE, accuracy analysis for various FFE scenarios, as well as a design space exploration leading to a fine-tuned and platform-dependent FFE customization. Our final implementation on a single Xilinx XC7VH580T FPGA device with GTZ transceivers can support a single link of up to 112 Gbps (56 GSa/s with PAM-4 modulation) and 2.26⋅10−6 Bit-Error-Rate.

This is a preview of subscription content, access via your institution.

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10

References

  1. 1.

    (2004). ITU-T recommendation G.975.1: Forward error correction for high bit-rate DWDM submarine systems. Tech. rep., Telecommunication Standardization Sector of ITU.

  2. 2.

    (2016a). https://industrial.panasonic.com/ww/products/electronic-materials/circuit-board-materials/megtron/megtron6.

  3. 3.

    (2016b). https://www.rogerscorp.com/acs/products/55/RO4350B-Laminates.aspx.

  4. 4.

    Alloatti, L., Palmer, R., Diebold, S., Pahl, K.P., Chen, B., Dinu, R., Fournier, M., Fedeli, J.M., Zwick, T., Freude, W., & et al. (2014). 100 GHz silicon–organic hybrid modulator. Light: Science & Applications, 3(5), e173.

    Article  Google Scholar 

  5. 5.

    Anslow, P. (2016). RS(544,514) FEC performance including precoding.

  6. 6.

    Apostolopoulos, D., Bakopoulos, P., Kalavrouziotis, D., Giannoulis, G., Kanakis, G., Iliadis, N., Spatharakis, C., Bauwelinck, J., & Avramopoulos, H. (2014). Photonic integration enabling new multiplexing concepts in optical board-to-board and rack-to-rack interconnects. In SPIE OPTO, International Society for Optics and Photonics (pp. 89,910D– 89,910D).

  7. 7.

    Bakopoulos, P., Dris, S., Argyris, N., Spatharakis, C., & Avramopoulos, H. (2016). 112 Gb/s sub-cycle 16-QAM Nyquist-SCM for intra-datacenter connectivity. In SPIE OPTO, International Society for Optics and Photonics (pp. 97,750A–97, 750A).

  8. 8.

    Barbosa, T.C., Moreno, R.L., Pereira, T.C., & Ferreira, L.H. (2010). FPGA implementation of a Reed-Solomon CODEC for OTN G. 709 standard with reduced decoder area. In 2010 6Th international conference on wireless communications networking and mobile computing, WiCOM (pp. 1–4): IEEE.

  9. 9.

    Caillaud, C., Adrover, M., Blache, F., Pommereau, F., Decobert, J., Jorge, F., Charbonnier, P., Konczykowska, A., Dupuy, J.Y., Mardoyan, H., & et al. (2015). Low cost 112 Gb/s inp DFB-EAM for PAM-4 2 km transmission. In European Conference on Optical communication (ECOC), 2015 (pp. 1–3): IEEE.

  10. 10.

    Chen, C., Tang, X., & Zhang, Z. (2015). Transmission of 56-Gb/s PAM-4 over 26-km single mode fiber using maximum likelihood sequence estimation. In Optical Fiber Communication Conference, Optical Society of America (pp. Th4A– 5).

  11. 11.

    Cheng, C., & Parhi, K.K. (2004). Hardware efficient fast parallel FIR filter structures based on iterated short convolution. In Proceedings of the 2004 International Symposium on Circuits and Systems, 2004, ISCAS’04, (Vol. 3 pp. III–361): IEEE.

  12. 12.

    Cheng, C., & Parhi, K.K. (2007). Low-cost parallel FIR filter structures with 2-stage parallelism. IEEE Transactions on Circuits and Systems I: Regular Papers, 54(2), 280–290.

    MathSciNet  Article  Google Scholar 

  13. 13.

    Cole, C. (2014). 400G Andamp; 4x100G SMF PMD alternatives study. Tech. rep., Finisar.

  14. 14.

    Cole, C., Lyubomirsky, I., Ghiasi, A., & Telang, V. (2013). Higher-order modulation for client optics. IEEE Communications Magazine, 51(3), 50–57.

    Article  Google Scholar 

  15. 15.

    Dris, S., Bakopoulos, P., Argyris, N., Spatharakis, C., & Avramopoulos, H. (2016). Scaling single-wavelength optical interconnects to 180 Gb/s with PAM-M and pulse shaping. In SPIE OPTO, International Society for Optics and Photonics (pp. 977,506–977,506).

  16. 16.

    Emeretlis, A., Kefelouras, V., Theodoridism, G., Nanou, M., Politi, C., Georgoulakis, K., & Glentis, G. (2015). FPGA implementation of a MIMO DFE in 40 Gb/s DQPSK optical links. In 2015 23rd European Signal Processing Conference EUSIPCO (pp. 1581–1585): IEEE.

  17. 17.

    Frlan, E. (2015). OIF’S CEI 56G interfaces–key building blocks for optics in the 400G data center. Tech. rep., Optical Internetworking Forum (OIF.

  18. 18.

    Georgis, G., Tzeranis, C., Reisis, D., & Synnefakis, G. (2014). XG-PON optical network unit downstream FEC design based on truncated Reed-Solomon code. In IEEE 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) (pp. 782–785).

  19. 19.

    Ghiasi, A. (2015). Large data centers interconnect bottlenecks. Optics express, 23(3), 2085–2090.

    Article  Google Scholar 

  20. 20.

    Iketani, S., & Nelson, B. (2013). Key factors influencing laminate material selection for today’s PCBs.

  21. 21.

    John, D., & Kipp, S.G. (2014). The 2015 Ethernet Roadmap.

  22. 22.

    Kachris, C., Kanonakis, K., & Tomkos, I. (2013). Optical interconnection networks in data centers: recent trends and future challenges. IEEE Communications Magazine, 51(9), 39– 45.

    Article  Google Scholar 

  23. 23.

    Kachris, C., Tzimpragos, G., Soudris, D., & Tomkos, I. (2014). Reconfigurable FEC codes for software-defined optical transceivers. In IEEE 2014 13th International Conference on Optical Communications and Networks (ICOCN) (pp. 1–4).

  24. 24.

    Kai, Y., Nishihara, M., Tanaka, T., Takahara, T., Li, L., Tao, Z., Liu, B., Rasmussen, J.C., & Drenski, T. (2013). Experimental comparison of pulse amplitude modulation (PAM) and discrete multi-tone (DMT) for short-reach 400-Gbps data communication. In 39Th european conference and exhibition on optical communication (ECOC), 2013.

  25. 25.

    Little, P. (2014). Who’s afraid of the big, bad DSP? Implementation of Advance Modulation for Single-Lambda Short-Reach Optical Interconnects.

  26. 26.

    Liu, M., Kuehn, W., Lu, Z., & Jantsch, A. (2009). Run-time partial reconfiguration speed investigation and architectural design space exploration. In IEEE 2009 International Conference on Field Programmable Logic and Applications (pp. 498–502).

  27. 27.

    Lyubomirsky, I., & Ling, W. (2014). Digital QAM modulation and equalization for high performance 400 Gbe data center modules. In Optical Fiber Communication Conference, Optical Society of America (pp. W1F–4).

  28. 28.

    Mirzaei, S., Hosangadi, A., & Kastner, R. (2007). FPGA implementation of high speed FIR filters using add and shift method. In IEEE International Conference on Computer Design, 2006, ICCD 2006 (pp. 308–313).

  29. 29.

    Mou, Z.J., & Duhamel, P. (1991). Short-length FIR filters and their use in fast nonrecursive filtering. IEEE Transactions on Signal Processing, 39(6), 1322–1332.

    Article  Google Scholar 

  30. 30.

    Parker, D.A., & Parhi, K.K. (1996). Area-efficient parallel FIR digital filter implementations. In IEEE Proceedings of International Conference on Application specific systems, architectures and processors, 1996, ASAP 96 (pp. 93–111).

  31. 31.

    Pfau, T., Kaneda, N., Corteselli, S., Leven, A., & Chen, Y.K. (2011). Real-time FPGA-based intradyne coherent receiver for 40 Gbit/s polarization-multiplexed 16-QAM. In Optical Fiber Communication Conference, Optical Society of America. p OTuN4.

  32. 32.

    Ren, J., Lee, H., Lin, Q., Leibowitz, B., Chen, E.H., Oh, D., Lambrecht, F., Stojanovic, V., Yang, C.K.K., & Zerbe, J. (2007). Precursor ISI reduction in high-speed I/O. In 2007 IEEE Symposium on VLSI Circuits (pp. 134–135): IEEE.

  33. 33.

    Sakib, M.N., & Liboiron-Ladouceur, O. (2013). A study of error correction codes for PAM signals in data center applications. IEEE Photonics Technology Letters, 25(23), 2274– 2277.

    Article  Google Scholar 

  34. 34.

    Scholten, M., Coe, T., Dillard, J., & Chang, F. (2009). Enhanced FEC for 40G/100G.

  35. 35.

    Stamoulias, I., Georgoulakis, K., Blionas, S., & Glentis, G. (2015). FPGA implementation of an MLSE equalizer in 10Gb/s optical links. In 2015 IEEE International Conference on Digital Signal Processing (DSP) (pp. 794–798): IEEE.

  36. 36.

    Szczerba, K., Westbergh, P., Karlsson, M., Andrekson, P.A., & Larsson, A. (2015). 70 Gbps 4-PAM and 56 Gbps 8-PAM using an 850 nm VCSEL. Journal of Lightwave Technology, 33(7), 1395–1401.

    Article  Google Scholar 

  37. 37.

    Taubenblatt, M. (2011). Optical interconnects for high performance computing. In Optical Fiber Communication Conference, Optical Society of America, p OThH3.

  38. 38.

    Tiwari, B., & Mehra, R. (2012). Design and implementation of Reed Solomon Decoder for 802.16 network using FPGA. In IEEE International Conference on Signal processing, computing and control (ISPCC), 2012 (pp. 1–5): IEEE.

  39. 39.

    Toft, F., Rousk, N., Mårtensson, J., Forzati, M., Olsson, B.E., & Larsson-Edefors, P. (2012). Feasibility study of FPGA-based equalizer for 112-Gbit/s optical fiber receivers. In 2012 IEEE International Symposium on Circuits and Systems (pp. 3234–3237): IEEE.

  40. 40.

    Torres, V., Perez-Pascual, A., Sansaloni, T., & Valls, J. (2012). Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA. In 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (pp. 408–411): IEEE.

  41. 41.

    Tsao, Y.C., & Choi, K. (2012). Area-efficient parallel FIR digital filter structures for symmetric convolutions based on fast FIR algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(2), 366–371.

    Article  Google Scholar 

  42. 42.

    Urricariet, C. (2015). Latest trends in data center optics. Tech. rep., Finisar.

  43. 43.

    Wang, Z., & Ghiasi, A. (2012). FEC Tradeofffs and analyses for 100G optical networking. Tech. rep., Broadcom.

  44. 44.

    Welch, B., Bergey-Luxtera, C., Ghiasi, A., Wang, Z., & Telang, V. (2016). 100 Gb/s Duplex Interconnects using Moderate PAM-N signaling.

  45. 45.

    Winters, J.H., & Kasturia, S. (1992). Adaptive nonlinear cancellation for high-speed fiber-optic systems. Journal of lightwave technology, 10(7), 971–977.

    Article  Google Scholar 

  46. 46.

    Woods, R., McAllister, J., Yi, Y., & Lightbody, G. (2008). FPGA-based implementation of signal processing systems: Wiley.

  47. 47.

    Yuan, F., Al-Taee, A.R., Ye, A., & Sadr, S. (2014). Design techniques for decision feedback equalisation of multi-giga-bit-per-second serial data links: a state-of-the-art review. IET Circuits Devices & Systems, 8(2), 118– 130.

    Article  Google Scholar 

  48. 48.

    Zergaïnoh, A., Duhamel, P., & Vidal, JP. (1997). Efficient implementation methodology of fast FIR filtering algorithms on DSP. Journal of VLSI signal processing systems for signal, image and video technology, 16(1), 81–103.

    Article  Google Scholar 

  49. 49.

    Zhang, M., Cui, Y., Li, Q., Han, W., Wang, L., & Liu, M. (2014). Implementation of Modified FEC Codec and High-Speed Synchronizer in 10g-EPON. Sensors & Transducers, 162(1), 117.

    Google Scholar 

Download references

Author information

Affiliations

Authors

Corresponding authors

Correspondence to Konstantinos Maragos or Christos Spatharakis or Panagiotis Kontzilas.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Maragos, K., Spatharakis, C., Lentaris, G. et al. A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s. J Sign Process Syst 88, 107–125 (2017). https://doi.org/10.1007/s11265-016-1201-y

Download citation

Keywords

  • FPGAs
  • Optical interconnects
  • Feedforward equalization
  • Parallel architectures
  • 112 Gb/s
  • Datacenters