A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators
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Images are often corrupted with noise during the image acquisition and transmission stage. Here, we propose a novel approach for the reduction of random-valued impulse noise in images and its hardware implementation on various state-of-the-art FPGAs. The presented algorithm consists of two stages in which the first stage detects whether pixels have been corrupted by impulse noise and the second stage performs a filtering operation on the detected noisy pixels. The human visual system is sensitive to the presence of edges in any image therefore the filtering stage consists of an edge preserving median filter which performs the filtering operation while preserving the underlying fine image features. Experimentally, it has been found that the proposed scheme yields a better Peak Signal-to-Noise Ratio (PSNR) compared to other existing median-based impulse noise filtering schemes. The algorithm is implemented using the high-level synthesis tool PARO as a highly parallel and deeply pipelined hardware design that simultaneously exploits loop level as well as instruction level parallelism with a very short latency of only few milliseconds for 16 bit images of size 512 × 512 pixels.
KeywordsFPGA Image denoising Noise detection Parallel architecture Random-valued impulse noise
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