Skip to main content
Log in

Embedded Real-Time H264/AVC High Definition Video Encoder on TI’s KeyStone Multicore DSP

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

To overcome high computational complexity of advanced video encoders for emerging applications that require real-time processing, multicore technology can be one of the promising solutions to meet this constraint. In this context, this paper presents a parallel implementation of the H264/AVC high definition (HD) video encoder exploiting the power processing of eight-core digital signal processor (DSP) TMS320C6678. GOP Level Parallelism approach is used to improve the encoding speed and meet the real-time encoding compliant. A master core is reserved to handle data transfer between the DSP and the camera interface via a Gigabit Ethernet link. Multithreading algorithm and ping-pong buffers technique are used to enhance the classic GOP level parallelism approach and hide communication overhead. Experimental results on seven slave DSP cores, running each at 1 GHz, show that our implementation allows performing a real-time HD (1280 × 720) video encoding. The achieved encoding speed is up to 28 f/s. The proposed parallel implementation accelerates the encoding process by a factor of 6.7 without inducing quality degradation in terms of PSNR or bit-rate increase compared to single core implementation. Experiments show that our proposed scheduling technique for hiding communication overhead saves up to 36 % of the fully encoding chain time which includes frames capturing, frames encoding and bitstream saving in a file.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8

Similar content being viewed by others

References

  1. Joint Video Team (JVT) of ISO/IEC MPEG & ITU-T VCEG (2013). Advanced video coding for generic audiovisual services. Avril 2013, http://www.itu.int/ITU-T/recommendations/rec.aspx?rec=11830&lang=en. Accessed Oct 2014.

  2. Xiao, Z., Le, S., & Baas, B. (2011). A fine-grained parallel implementation of a H.264/AVC encoder on a 167-processor computational platform. Pacific Grove, CA: ACSSC 2011.

    Book  Google Scholar 

  3. Ming-Jiang Yang, Jo-Yew Tham, Rahardja, S., Da-Jun Wu. Real-time H.264 encoder implementation on a low-power digital signal processor, in Multimedia and Expo, 2009. ICME 2009. IEEE International Conference on , vol., no., pp.1150-1153, June 28 2009-July 3 2009. doi:10.1109/ICME.2009.5202703.

  4. Elhamzi, W., Dubois, J., Miteran, J., Atri, M., Heyrman, B., & Ginhac, D. (2013). Efficient smart-camera accelerator: a configurable motion estimator dedicated to video codec. Journal of Systems Architecture, 59(10, Part A), 870–877. ISSN 1383–7621.

    Article  Google Scholar 

  5. Jo, S., Jo, S. H., & Song, Y. H. (2012). Exploring parallelization techniques based on OpenMP in H.264/AVC encoder for embedded multi-core processor. Journal of Systems Architecture, 58(9), 339–353.

    Article  Google Scholar 

  6. Zrida, H. K., Ammari, A. C., Jemai, A., & Abid, M. (2011). High level optimized parallel Specificationof a H.264/AVC video encoder. International Journal of Computing and Information Sciences, 9(1), 34–46.

    Google Scholar 

  7. TMS320C6000 DSP Cache User’s Guide. http://www.ti.com/lit/ug/spru656a/spru656a.pdf. Accessed Oct 2014.

  8. Sankaraiah, S., Lam, H. S., Eswaran, C., & Abdullah, J. (2011). GOP level parallelism on H.264 video encoder for multicore architecture. In International Conference on Circuits, System and Simulation IPCSIT. Singapore: IACSIT Press.

    Google Scholar 

  9. Sankaraiah, S., Shuan, L. H., Eswaran, C., & Abdullah, J. (2013). Performance optimization of video coding process on multi-core platform using Gop level parallelism. International Journal of Parallel Programming. doi:10.1007/s10766-013-0267-4. ISSN:1573–7640.

    Google Scholar 

  10. Rodriguez, A., Gonzalez, A., Malumbres, M.P. Hierarchical Parallelization of an H.264/AVC Video Encoder, in Parallel Computing in Electrical Engineering, 2006. PAR ELEC 2006. International Symposium on, vol., no., pp.363-368, 13-17 Sept. 2006. doi:10.1109/PARELEC.2006.42.

  11. Fang Ji, Xing-yuan Li, Chang-long Yang. An Algorithm Based on AVS Encoding on FPGA Multi-Core Pipeline, in Computational and Information Sciences (ICCIS), 2013 Fifth International Conference on, vol., no., pp. 1521-1524, 21-23 June 2013. doi:10.1109/ICCIS.2013.400.

  12. Zhuo Zhao, Ping Liang. A Highly Efficient Parallel Algorithm for H.264 Video Encoder, in Acoustics, Speech and Signal Processing, 2006. ICASSP 2006 Proceedings. 2006 IEEE International Conference on, vol.5, no., pp.V-V, 14-19 May 2006. doi:10.1109/ICASSP.2006.1661319.

  13. H264/AVC software Joint Model JM. http://iphome.hhi.de/suehring/tml/download/old_jm/. Accessed Oct 2014.

  14. Yen-Kuang Chen, Tian, X., Steven Ge, Girkar, M. Towards efficient multi-level threading of H.264 encoder on Intel hyper-threading architectures, in Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International, vol., no., pp.63-, 26-30 April 2004. doi:10.1109/IPDPS.2004.1302990.

  15. Lehtoranta, O., Hämäläinen, T., Lappalainen, V., & Mustonen, J. (2002). Parallel implementation of video encoder on quad DSP system. Microprocessors and Microsystems, 26(1), 1–15.

    Article  Google Scholar 

  16. Sun, S., Wang, D., & Chen, S. (2007). A highly efficient parallel algorithm for H.264 encoder based on macro-block region partition. In R. Perrott, B. Chapman, J. Subhlok, R. Mello, & L. Yang (Eds.), High performance computing and communications (Vol. 4782, pp. 577–585). Berlin: Springer.

    Chapter  Google Scholar 

  17. Shenggang Chen, Shuming Chen, Huitao Gu, Hu Chen, Yaming Yin, Xiaowen Chen, Shuwei Sun, Sheng Liu, Yaohua Wang. Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform, in High Performance Computing and Communications (HPCC), 2010 12th IEEE International Conference on, vol., no., pp. 465-470, 1-3 Sept. 2010. doi:10.1109/HPCC.2010.82.

  18. Yu-Wen Huang, Tung-Chien Chen, Chen-Han Tsai, Ching-Yeh Chen, To-Wei Chen, Chi-Shi Chen, Chun-Fu Shen, Shyh-Yih Ma, Tu-Chih Wang, Bing-Yu Hsieh, Hung-Chi Fang, Liang-Gee Chen. A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications, in Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, vol., no., pp. 128-588 Vol. 1, 10-10 Feb. 2005 doi: 10.1109/ISSCC.2005.1493902

  19. Su, H., Wen, M., Wu, N., Ren, J., & Zhang, C. (2014). Efficient parallel video processing techniques on GPU: from framework to implementation. The Scientific World Journal, 2014, 716020. 19 pages.

    Google Scholar 

  20. António Rodrigues, Nuno Roma, and Leonel Sousa. 2010. p264: open platform for designing parallel H.264/AVC video encoders on multi-core systems. In Proceedings of the 20th international workshop on Network and operating systems support for digital audio and video (NOSSDAV '10). ACM, New York, NY, USA, 81-86. doi:10.1145/1806565.1806586.

  21. Adeyemi-Ejeye, A. O., & Walker, S. (2014). 4kUHD H264 wireless live video streaming using CUDA. Journal of Electrical and Computer Engineering, 2014, 183716. doi:10.1155/2014/183716. 12 pages.

    Article  Google Scholar 

  22. TMS320C6678 multicore fixed and floating-point digital signal processor data manual. Literature Number: SPRS691D April 2013, http://www.mouser.com/ds/2/405/sprs691d-256638.pdf. Accessed Oct 2014.

  23. BeagleBoard-xM Rev C system Reference Manual. http://beagleboard.org/static/BBxMSRM_latest.pdf. Accessed Oct 2014.

  24. Banana Pro web site. http://www.lemaker.org/. Accessed Jan 2015.

  25. TI Network Developer’s Kit (NDK) v2.21 User’s Guide. http://www.ti.com/lit/ug/spru523h/spru523h.pdf. Accessed Oct 2014.

  26. Open source computer vision library. http://opencv.org/. Accessed Oct 2014.

  27. SYS/BIOS and Linux Multicore Software Development Kits (MCSDK) for C66x, C647x, C645x Processors. http://www.ti.com/tool/bioslinuxmcsdk. Accessed Oct 2014.

  28. Werda, I., Kossentini, F., Ayed, M.B., Massmoudi, N. Analysis and Optimization of UB Video’s H.264 Baseline Encoder Implementation on Texas Instruments’ TMS320DM642 DSP, in Image Processing, 2006 IEEE International Conference on, vol., no., pp. 3277-3280, 8-11 Oct. 2006. doi:10.1109/ICIP.2006.312785.

  29. Bahri, N., Werda, I., Grandpierre, T., Ben Ayed, M., Masmoudi, N., & Akil, M. (2013). Optimizations for real-time implementation of H264/AVC video encoder on DSP processor. International Review on Computers and Software (IRECOS), 8(9), 2025–2035.

    Google Scholar 

  30. Joint Video Team (JVT) of ISO/IEC MPEG & ITU-T VCEG organizations. http://www.itu.int/en/ITU-T/studygroups/com16/video/Pages/jvt.aspx. Accessed Oct 2014.

  31. Bahri, N., Werda, I., Samet, A., Ayed, M. A. B., & Masmoudi, N. (2012). Fast intra mode decision algorithm for H264/AVC HD baseline profile encoder. International Journal of Computer Applications, 37(6), 8–13.

    Article  Google Scholar 

  32. Werda, I., Chaouch, H., Samet, A., Ayed, M. A. B., & Masmoudi, N. (2010). Optimal DSP based integer motion estimation implementation for H.264/AVC baseline encoder. The International Arab Journal of Information Technology – IAJIT, 7(1), 96–104.

    Google Scholar 

  33. C6678 power spreadsheet. http://www.ti.com/lit/zip/sprm545. Accessed Oct 2014.

  34. Power consumption summary for keystone C66x devices. http://www.ti.com/lit/an/sprabi5a/sprabi5a.pdf. Accessed Oct 2014.

  35. C6678 power spreadsheet. http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/171805.aspx. Accessed Oct 2014.

  36. Nissim Saban. Multicore DSP Vs GPUs, [online available]: http://www.sagivtech.com/contentManagment/uploadedFiles/fileGallery/Multi_core_DSPs_vs_GPUs_TI_for_distribution.pdf

Download references

Acknowledgements

This work is fruit of cooperation between Sfax National School of Engineers and ESIEE PARIS Engineering School. It is sponsored by the French ministries of Foreign Affairs and Tunisian ministry for Higher Education and Scientific Research in the context of Hubert Curien Partnership (PHC UTIQUE) under the CMCU project number 12G1108.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Nejmeddine Bahri.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Bahri, N., Grandpierre, T., Ayed, M.A.B. et al. Embedded Real-Time H264/AVC High Definition Video Encoder on TI’s KeyStone Multicore DSP. J Sign Process Syst 86, 67–84 (2017). https://doi.org/10.1007/s11265-015-1098-x

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-015-1098-x

Keywords

Navigation