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Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing

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Abstract

This paper proposes a cost-effective and variable-channel floating-point fast independent component analysis (FastICA) hardware architecture and implementation for EEG signal processing. The Gram-Schmidt orthonormalization based whitening process is utilized to eliminate the use of the dedicated hardware for eigenvalue decomposition (EVD) in the FastICA algorithm. The proposed two processing units, PU1 and PU2, in the presented FastICA hardware architecture can be reused for the centering operation of preprocessing and the updating step of the fixed-point algorithm of the FastICA algorithm, and PU1 is reused for Gram-Schmidt orthonormalization operation of preprocessing and fixed-point algorithm to reduce the hardware cost and support 2-to-16 channel FastICA. Apart from the FastICA processing, the proposed hardware architecture supports re-reference, synchronized average, and moving average functions. The cost-effective and variable-channel FastICA hardware architecture is implemented in 90 nm 1P9M complementary metal-oxide-semiconductor (CMOS) process. As a result, the FastICA hardware implementation consumes 19.4 mW at 100 MHz with a 1.0 V supply voltage. The core size of the chip is 1.43 mm2. From the experimental results, the presented work achieves satisfactory performance for each function.

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Acknowledgments

This work was supported in part by the Ministry of Science and Technology (MOST) Grants MOST 103-2221-E-009-099-MY3 and MOST 103-2911-I-009-101, and in part by Contract: 104W963. The authors thank Chip Implementation Center for their support.

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Authors and Affiliations

  1. Department of Computer Science, National Chiao Tung University, Hsinchu, Taiwan, 300, Republic of China

    Lan-Da Van, Po-Yen Huang & Tsung-Che Lu

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  1. Lan-Da Van
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  2. Po-Yen Huang
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  3. Tsung-Che Lu
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Correspondence to Lan-Da Van.

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Van, LD., Huang, PY. & Lu, TC. Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing. J Sign Process Syst 82, 91–113 (2016). https://doi.org/10.1007/s11265-015-0988-2

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