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A Family of Modular QRD-Accelerator Architectures and Circuits Cross-Layer Optimized for High Area- and Energy-Efficiency

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Abstract

QR-decomposition accelerators are attractive SoC components for many applications with a wide range of specifications. A new family of highly area- and energy-efficient, modular two-way linear-array QRD architectures based on the Givens algorithm and CORDIC rotations is proposed. The template architecture allows for implementations of real-/complex-valued and integer/floating-point QRDs. An accurate algebraic cost model enables cross-layer optimization over architecture, micro-architecture and circuit level using a rich set of parameters. Quantitative results for exemplary applications are presented for implementations in 40-nm CMOS, proving the significant improvement of efficiency.

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Acknowledgments

The authors would like to thank their colleague Jos Huisken for many discussions and helpful comments as well as Eqbal Maraqa for his highly valuable contributions in the validation of the cost model.

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Authors and Affiliations

  1. Chair of Electrical Engineering and Computer Systems, RWTH Aachen University, Schinkelstrasse 2, D-52062, Aachen, Germany

    Upasna Vishnoi, Michael Meixner & Tobias G. Noll

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  1. Upasna Vishnoi
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  2. Michael Meixner
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  3. Tobias G. Noll
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Correspondence to Upasna Vishnoi.

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Vishnoi, U., Meixner, M. & Noll, T.G. A Family of Modular QRD-Accelerator Architectures and Circuits Cross-Layer Optimized for High Area- and Energy-Efficiency. J Sign Process Syst 83, 329–356 (2016). https://doi.org/10.1007/s11265-015-0976-6

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  • DOI: https://doi.org/10.1007/s11265-015-0976-6

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