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A Configurable Architecture for Fast Moments Computation


In this paper, we present a single-chip architecture for generating a full set of geometric moments using digital filters. Other types of moments such as Zernike and Tchebichef moments can also be implemented. The architecture can be configured for any order of geometric moments and image spatial resolution at run time. The use of a single-scaler method and reusable hardware resources enables higher order moments to be computed. The incorporation of two-level pipelining and masking techniques further increases the throughput. Realized in a field-programmable gate array, the design is capable of processing sixty 512 × 512 8-bit-pixel images per second at 20 MHz, generating (59 + 59) orders of geometric moments (3,600 moments). The maximum round-off error is approximately 1 %.

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Correspondence to Kah-Hyong Chang.

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Chang, KH., Paramesran, R. A Configurable Architecture for Fast Moments Computation. J Sign Process Syst 78, 179–186 (2015).

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  • Image processing
  • Moments
  • Digital filters
  • Real-time
  • Configurable
  • High-order
  • Field-Programmable Gate Array (FPGA)